Zuken and Aldec launched CADSTAR FPGA, which is a collaborative product for complete FPGA design and verification. CADSTAR FPGA combines Aldec’s Active-HDL Lite verification tool and Zuken’s desktop PCB design suite, CADSTAR, allowing engineers to perform mixed language simulation for vendor neutral FPGAs within the CADSTAR environment.

The relationship between the FPGA and PCB design processes is a primary area where synchronization can deliver opportunities for increased efficiency in the design process. CADSTAR FPGA technology is structured on integration of FPGA design within the PCB layout. The concurrent and collaborative process that this tool provides is made simple using an intuitive easy-to-use Design Flow Manager. This eliminates manual movement and back-annotation requirements, reducing time to market while increasing output of right-first-time designs.

CADSTAR FPGA combines Aldec’s Active-HDL Lite design simulation environment and Zuken’s desktop PCB design suite, CADSTAR. Engineers can perform comprehensive FPGA designs with complete support for technology from multiple FPGA vendors including Actel, Altera, Lattice, Quicklogic and Xilinx. It also performs mixed VHDL and Verilog simulation, strictly adhering to the latest IEEE language standards.

CADSTAR FPGA provides one universal project manager that controls all design files for simulation, synthesis, place and route and pin assignment to the PCB. This integrated solution supports robust I/O synchronization between the FPGA device and the PCB, helping to optimize the routing pattern for high-density devices like BGAs.

More info:
Zuken, Aldec Launch CADSTAR FPGA