Orange Tree ZestET1 Programmable Interconnect Module

The ZestET1, from Orange Tree Technologies, is the latest generation of the Zest Series programmable interconnect modules. The ZestET1 features a dedicated hardware TCP/IP Offload engine (TOE) and a companion FPGA for universal Ethernet interfacing. The module comes in a compact 75mm x 50mm form factor. The ZestET1 offers sustained data rates of over 200MBytes/s and latency of 6µsec. The modules offer Gigabit Ethernet performance for real-time applications without having to integrate complex networking hardware and software. Its scalability, performance, foot print, cost, and ease-of-use provide a unique set of capabilities backed up by the hardware reliability of the GigEx TOE and the flexibility and programmability of the companion FPGA.

ZestET1 Programmable Interconnect Module - Orange Tree Technologies

The ZestET1 features Orange Tree’s GigExpedite (GigEx) hardware TCP/IP stack — including hardware UDP and TCP/IP Offload Engine (TOE). The GigEx device removes the network protocol processing burden from the CPU or companion FPGA. Resource intensive memory copies, checksum computation and reassembling of out-of-order packets are handled by the GigEx device. This enables a smaller, lower cost CPU to be deployed in the system or a soft-core processor implemented within the companion FPGA. Processor resources are allocated to running applications rather than handling network traffic.

The companion FPGA provides a Universal Interface for the multiple Ethernet variations. It can be used to build upon the core communications protocols provided by the GigEx device (IPv4, TCP, UDP, DHCP Client, Auto IP, UPnP, HTTP, ARP). It can be quickly and cost-effectively extended to implement application layer protocols such as GigE Vision and the family of Industrial Ethernet standards. This results in a common production platform that can be applied to multiple projects and multiple Ethernet standards.

The on-board companion FPGA is a Xilinx Spartan-3A XC3S1400A with 1.4M system gates that are completely free for user programming. The FPGA is supported with 64MBytes DDR SDRAM, can be programmed from on-board Flash, Ethernet or JTAG and is capable of running soft-core processors and higher level protocols such as GigE Vision and Industrial Ethernet. The FPGA provides a programmable interface to external devices via the 80 pins of user IO and is used for processing and formatting of data to be streamed over the Ethernet interface. IThe use of a socket interface and register interface remove the cost and integration headache of PCI type interfacing and allows more of the FPGA logic to be dedicated to processing tasks.

More information: Orange Tree