KaiSemi Automated FPGA-to-ASIC Conversion Process

According to KaiSemi, a breakthrough in automated FPGA-to-ASIC conversion enables them to provide companies with a seamless full turnkey ASIC solution that results in fully compatible replacement chips. KaiSemi’s process automatically converts directly from the original FPGA netlist into a functionally-identical ASIC gate-level netlist. KaiSemi’s automated conversion uses a database of proven standard-cell fab process libraries and standard cores. The libraries enable the conversion of any type and size of FPGA from any FPGA vendor. The resulting ASIC devices consume less power and cost up to 70% less than their FPGA counterparts.

KaiSemi's automated FPGA-to-ASIC conversion process

KaiSemi’s Automated FPGA-to-ASIC Conversion Process Highlights

  • Zero-NRE model: customers doesn’t pay in advance for the one time design cost known also as Non Recurrent Engineering (NRE)
  • Backed by a tier-one fab vendor (probably Toshiba, but they also support TowerJazz, NEC, UMC and SMIC)
  • Utilizes a database of proven standard-cell fab process libraries and standard cores
  • Libraries enable the conversion of any type and size of FPGA from any FPGA vendor
  • Cost optimization during the automated conversion
  • Resulting ASICs are pin-compatible, timing-compatible, and functionally identical to the original FPGA devices
  • Resulting ASIC devices consume less power and cost up to 70% less than their FPGA counterparts
  • Eliminates the need for customer involvement and resources, NRE costs, long lead times, and the risks that are part of traditional FPGA-to-ASIC conversion flows
  • KaiSemi manages the whole FPGA-to-ASIC process for customers (purchase order, ASIC flow, manufacturing, shipment of the ASIC chips)
  • Enables customers to order an ASIC chip as if it was an off-the-shelf second-source replacement chip with a relatively short lead-time

More info: KaiSemi