PLDA introduced the XpressRich3 IP core for FPGAs and ASICs based on the forthcoming PCIe 3.0 specification, currently under development within the PCI-SIG. The PLDA XpressRich3 core features an architecture that seamlessly allows both ASIC and FPGA implementations. The PLDA XpressRich3 IP will be available for review at the PCI-SIG Developers Conference, which will be held on June 23-24, 2010 in Santa Clara, California.
The PLDA XpressRich3 core includes configurable features and a range of user interface options to help achieve simple to more complex design requirements. The PLDA XpressRich3 IP core is also fully compatible with the Intel PIPE 3.0 interface and integrates with PIPE-compliant Gen3 PHYs.
PLDA XpressRich3 IP Core Features
- Flexible x1, x2, x4 and x8 PCI Express Core
- Link rate of 2.5, 5.0 and 8.0 Gbps per lane for blazing performance
- Width-configurable PIPE 3.0 Interface, delivering easy PHY integration
- Customization using PLDA’s IP Wizard customization tool
- Technical support from the IP designers
More info: PLDA