Xilinx, Inc. (Nasdaq: XLNX) announced their Virtex(TM)-5 solution for designers using the XAUI communications protocol. The solution includes a reference design, XAUI protocol characterization report for GTP transceivers, access to Xilinx(R) LogiCORE(TM) IP, and a PCIe(R) add-in card with CX4 connector development board. The solution accelerates time-to-market for architects developing and implementing high speed designs using the XAUI protocol for applications in communications, networking, storage, computing, and aerospace and defense markets. The solution enables engineers to quickly get a design using XAUI up and running on a desktop PC, including all components needed to bring-up a high performance Virtex-5 FPGA based XAUI design in a PC environment.
Complete XAUI Solution
- 8-lane PCI Express add-in card with a CX4 connector
- Virtex-5 FPGA with built-in blocks for PCI Express endpoint, Ethernet MACs & 3.75 Gbps RocketIO GTP transceivers
- LogiCORE IP products to develop a XAUI, XGMAC, 1-8-lane PCIe endpoint in the FPGA
- Reference Designs and Software
- Windows and Linux software drivers
- Technical documentation
Xilinx Virtex-5 FPGAs, with built-in endpoint blocks for PCI Express(R), Ethernet MAC and low power 3.75Gbps RocketIO(TM) GTP transceivers, and numerous LogiCORE soft IP — including XGMAC (Ten Gigabit Ethernet MAC) and XAUI, provide a platform that enables implementation of a fully integrated and compliant solution that has passed the UNH-IOL testing for the XAUI protocol.
More info: Virtex-5 FPGA Reference Design for XAUI