Seminars: ASIC, ASSP and SoC Verification Using FPGAs

Synplicity, Inc. (NASDAQ:SYNP) and Xilinx, Inc. (NASDAQ:XLNX) will staging seminars for ASIC and ASSP designers. The technical and educational seminar will present industry-leading design and verification methodologies and provide valuable information to help designers save time and money on current and future design projects. the event will discuss and compare different verification methodologies and will present justification for why the use of FPGA-based prototyping can save valuable time and money on current or future ASIC, ASSP or SoC projects.

The seminar will cover:

  • Why use FPGA prototypes
  • Choosing an FPGA technology
  • Board-level design considerations
  • Build’n'buy choices for the FPGA board
  • Making the ASIC design FPGA ready
  • Getting onto the board
  • In-system debug
  • Fixing bugs and quick iteration

This free seminar series will be held in locations throughout Europe, North America and Asia Pacific. Current schedule for Europe:

  • 4 October 2007 – Cambridge, UK
  • 11 October 2007 – Paris, France
  • 15 October 2007 – Munich, Germany
  • 23 October 2007 – Hertzliya, Israel
  • 23 October, 2007 – Stockholm, Sweden
  • November TBD, 2007 – Eindhven, Nederlands

The seminars target:

  • ASIC, ASSP and FPGA designers
  • Verification engineers
  • System architects
  • Engineering and project managers

More info:
Synplicity, Xilinx Announce Worldwide ASIC Verification Seminars
New Approaches To Accelerate ASIC, ASSP and SoC Verification Using FPGAs