Xilinx SPI-4.2 and SFI-4.1 Solutions
Xilinx Inc. (Nasdaq: XLNX) has developed solutions for the Optical Internetworking Forum (OIF) System Packet Interface (SPI) 4.2 and SerDes Framer Interface (SFI) 4.1 standards, the industry’s highest performance channelized packet interfaces. Xilinx’s solutions are based on Virtex(TM)-5 LXT FPGAs and feature the ML550 hardware verification board, SPI-4.2 LogiCORE(TM) IP, and SFI-4.1 reference design. Verified across multiple FPGA platforms, the solutions accelerate the design cycle of wired networking systems that require OC-192 (10 Gbps), multiple OC-48 (2.5 Gbps) or 10 Gbps Ethernet interfaces, resulting in much faster time-to-market than competing solutions.
Xilinx ML550 Board
The Xilinx ML550 board is ideal for development and evaluation of OIF and other networking interfaces. It enables designers to implement high-speed applications with extreme flexibility. Xilinx ChipSync(TM) technology, available only in Virtex-5 FPGAs, provides accurate dynamic alignment of clock and data using 75 ps programmable delays, enabling improved timing and reliable operation under changing system conditions. The Xilinx ML550 board includes:
- Virtex-5 ML550 Networking Interfaces Development Board
- 5V/6.5A DC power supply
- Power supply line cord
- USB B-to-A cable
- Xilinx LVDS loopback board
- Documentation and reference design CD-ROM
- SystemACE CompactFlash card
- Misc. Xilinx promo kits and documentation
Xilinx SPI-4.2 LogiCORE IP
The Xilinx SPI-4.2 LogiCORE(TM) IP interconnects physical layer ASSPs to link layer FPGA devices in a wide range of networking applications and multi-service DWDM and SONET/SDH-based transport systems. The Xilinx SPI-4.2 IP core provides proven interoperability with industry leading ASSPs and provides up to 20% higher data bandwidth due to optimized payload efficiencies as compared to competing FPGA offerings. SPI LogiCORE solutions support OC-192 (10 Gbps) and OC-48 (2.5 Gbps) data rates. Xilinx SPI cores:
- Fully comply with the latest Optical Internetworking Forum’s (OIF) System Packet Interface (SPI) implementation agreements
- Fully comply with the SATURN® Development Group’s POS-PHY interface specifications
- Enable OC-48/OC-192 POS, ATM, Gb and 10 Gbps Ethernet applications
- Are verified in hardware to interoperate with link-layer, PHY and NPU devices from companies such as PMC-Sierra, Mindspeed, Vitesse, and Intel®
Xilinx SFI-4.1 Reference Design
The Xilinx SFI-4.1 reference design supports up to 710 Mbps/channel with dynamic alignment to provide a robust solution for OC-192 framer interfaces. These reference designs:
- Fully comply with the latest Optical Internetworking Forum’s (OIF) SerDes Framer Interface (SFI) 4.1 specification.
- Are verified in hardware.
The SFI-4.1 reference design is immediately available free of charge. The SPI-4.2 LogiCORE IP is available for a free evaluation and can be purchased for an $18,000 site license fee. The Virtex-5 LXT FPGA ML550 board is available for $2,200.
More info: SPI-4.2 LogiCORE IP | Virtex-5 LXT FPGA ML550 Board
If you found this page useful, bookmark and share it on:
Possibly of Interest
- Xilinx SFI-5 Interface Reference Design
- Virtex-5 FPGA Solution for XAUI Communications Protocol
- Xilinx 400 Mbps DDR2 SDRAM Interface Reference Design
- Xilinx Ethernet AVB Endpoint LogiCORE IP Core
- Xilinx CPRI and OBSAI LogiCORE IP Solutions
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
