Flexras Technologies introduced version 3.2 of the Wasga Compiler Design Suite for FPGA-based prototyping. The new version of the tool supports the Xilinx Virtex-7 FPGA and includes new features that accelerate SoC rapid prototyping. Wasga Compiler is a timing-driven partitioning tool for SoC rapid prototyping that automatically partitions large designs onto multiple FPGAs while addressing chip resources, connectivity, and the clock frequency constraints required for running software applications in near real time. Release 3.2 of the tool is available now.
Wasga Compiler v3.2 supports the Vivado Design Suite and the Virtex-7 FPGA platform. Wasga Compiler enables very fast prototyping of complex SoCs. It achieves efficient results in days, or even hours. The tool offers timing-driven automatic partitioning and high speed Virtex-7 FPGA Advanced Pin Multiplexing (APM) IP for inter-FPGA communications.
The Wasga Compiler Design Suite supports Dini boards, including the DNV7F2A. It is also included in Reflex’s FPP25 offering. According to Flexras, semiconductor companies using off-the-shelf or in-house custom boards that include Virtex-7 and other FPGAs are already benefiting from the latest development tool.
Wasga Compiler v3.2 Features
- Virtex-7 FPGA Advanced Pin Multiplexing IPs (APM) using Serdes and LVDS
- Automatic generation of XDC pin-planning and timing constraints for Vivado Design Suite
- Logic replication and pruning to optimize connectivity between FPGAs
- Modeling of inter-FPGA configurable cables