Xilinx Acquires Modelware, Debuts 100G Traffic Management Reference Design

Xilinx has acquired Modelware, which is a provider of traffic management/packet processing silicon intellectual property (IP) cores and reference designs that simplify system development and enable greater differentiation for networking applications supporting 10G, 40G, 100G and beyond. Xilinx also announced a FPGA-based 100G traffic management reference design for speeding evaluation and implementation of high bandwidth packet processing applications.

Xilinx’s Modelware Acquisition Highlights

  • Modelware is a provider of traffic management/packet processing silicon intellectual property (IP) cores and reference designs
  • Acquisition provides designers with a one stop shop for addressing high bandwidth challenges, million-connection-network needs, and enabling system capabilities that satisfy evolving demands for Quality of Service
  • Acquisition strengthens Xilinx’s ability to deliver FPGA-optimized packet processing, switching, and traffic management solutions that address very granular (trending to 1+ million queues) per-flow bandwidth provisioning, and scalable high-bandwidth traffic aggregation capabilities (20G to 100G and beyond) across the service provider, enterprise networking and data center markets
  • Modelware has the only FPGA-based IP capable of scaling to up to 100G + and running traffic rates at 150 million packets-per-second with 64B packet size on a single FPGA
  • Modelware’s solutions consists of very scalable, highly optimized IP cores tuned for Xilinx Field Programmable Gate Array devices and deployed for packet processing, switching, and traffic management systems
  • Modelware technology encompasses several legacy cores such as HDLC, ATM, PWE3
  • Xilinx will continue to use legacy cores to support legacy installations such as the mobile backhaul spac
  • Xilinx will help engineers maintain existing deployments and offer an easy migration path from TDM to all-IP solutions without a need for new hardware

More info: Xilinx