Xilinx, Inc. (Nasdaq: XLNX) announced immediate availability of its low cost Spartan(TM)-3A FPGA development kit for DDR2 SDRAM interfaces, the Virtex(TM)-5 FPGA development platform (ML-561) for multiple high-performance memory interfaces (I/Fs), and the memory interface generator (MIG) software version 1.7. These complete solutions enable FPGA users to quickly implement and verify custom memory interface designs across various data rates and bus widths thus accelerating time-to-market.
The solutions, including device characterization, data capture circuitry, and memory controller, are all fully verified in hardware using memory devices from industry leaders such as Micron Technology.
Production-qualified 90nm Spartan-3A and 65nm Virtex-5 FPGAs, supporting up to twice the bus-width of any other FPGA based solution shipping today. Low cost memory interfaces can be built rapidly with the I/O optimized Spartan-3A FPGA family while Virtex-5 FPGAs with built-in 75 ps calibration circuits, flexible I/Os to connect memory on any side of the FPGA, and innovative packaging to minimize crosstalk for reliable operation of wide memory interfaces offer the highest bandwidth.
The Spartan-3A FPGA development kit for DDR2 SDRAM interfaces allows designers to get a DDR2 SDRAM interface up and running right out-of-the box in less than an hour. The development kit includes all components needed to complete a low-cost design.
The Virtex-5 FPGA based development platform (ML561) features multiple high-performance memory interfaces and hardware-verified reference designs with in-depth ChipScope Pro demonstration files to enable implementation and verification of the highest bandwidth memory I/Fs.
The MIG is a free, user-friendly parameterizable software tool to create memory interface designs in unencrypted RTL for Xilinx FPGAs, DDR2/DDR SDRAM, QDR II SRAM, and RLDRAM II interfaces. MIG supports multiple memory architectures, device and package combinations that provide system designers with the flexibility to easily customize their own design. The MIG is integrated in the Xilinx CORE Generator software and provides RTL source and constraints files through a graphical interface for ultimate user flexibility. The designs are generated in a modular format to provide distinct physical layer, user interface and controller blocks providing users with simplified verification capabilities.
The Spartan-3A development kit for DDR2 SDRAM interface is immediately available for US$235. Free download of RTL source reference designs and the Memory Interface Generator (MIG) version 1.7 are immediately available. The Virtex-5 FPGA based ML-561 platform is immediately available for US$5,995.