TEK QuiXilica Tarvos-V5 VXS

TEK Microsystems introduced the QuiXilica Tarvos-V5 VXS 6U ANSI/VITA 41 (VXS) compliant high-speed digitizer board. The Tarvos-V5 combines high density FPGA processing with six 16-bit A/D input channels at 185 Msps (Megasamples per second) along with a coherent 16-bit D/A output channel. The QuiXilica Tarvos-V5 VXS features three Xilinx Virtex-5 FPGAs. The Tarvos-V5 offers a measured signal-to-noise ratio (SNR) of 72 dBFS and Spurious Free Dynamic Range (SFDR) in excess of 95 dB. The board is ideal for high channel count signal processing for a wide range of applications — such as RADAR, signals and electronic intelligence (SIGINT / ELINT), and Electronic Warfare (EW). The Tarvos-V5 VXS is available now, with delivery from stock to 8 weeks ARO.

QuiXilica Tarvos-V5 VXS Digitizer Board - TEK Microsystems

The architecture of the Tarvos-V5 combines six analog input channels with three Xilinx Virtex-5 FPGAs, providing up to 2,336 DSP slices and 1.285 TeraMAC/s of signal processing, equivalent to 61% of a Xilinx Virtex-5 SX95T device per input channel. For high channel count requirements such as beamforming, direction finding, jamming or anti-jam / interference cancellation, common in RADAR, SIGINT, communications, and EW applications, the Tarvos-V5 provides both the highest processing density per channel and per 6U slot, reducing total size, weight and power for many systems.

Tarvos-V5 Overview

  • Features three Xilinx Virtex-5 FPGAs, advanced DDR3 SDRAM, and the highest resolution digital-to-analog and analog-to-digital converter technologies available at a 185 Msps sampling rate
  • Each analog input channel uses a Linear Technology LTC2209 16-bit A/D converter, which is designed for digitizing high frequency, wide dynamic range signals within an analogue input bandwidth of 700 MHz
  • A range of options are available for input signal conditioning to support different receiver applications
  • The output channel uses a Maxim MAX5891 16-bit D/A converter that is synchronized to the input clock rate and the output is AC coupled with full scale output voltage of -2 dBm into a 50 ohm load
  • Features high bandwidth, low latency interconnect paths between its FPGAs which has been carefully specified to ensure that data from any analog channel can be broadcast to all FPGAs to support processing that relies on simultaneous access to data from all channels
  • Employs the latest flexible I/O communication modules (SFP+ and QSFP)
  • Available for a wide range of operating environments, including commercial grade as well as rugged air and conduction cooled to support

More info: TEK Microsystems, Incorporated