Serial RapidIO Gen 2 v1.2 Endpoint, CPRI v4.1, and JESD204B v.1.1 IP Cores

Xilinx recently introduced the Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE, CPRI v4.1 LogiCORE, and JESD204B v.1.1 LogiCORE IP cores. The Xilinx three LogiCORE IP cores support connectivity standards and will help developers address design challenges in building new wireless equipment with higher system capacities. The Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP, JESD204 v1.1 LogiCORE IP , and CPRI v4.1 LogiCORE IP are ideal for building programmable, flexible and cost effective 3G+/4G wireless base stations. They are available in Xilinx’s ISE Design Suite 13.3 and can be evaluated free of charge.

Xilinx Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP
This core is designed to the RapidIO Trade Association’s RapidIO Gen 2.2 specification. It is the industry’s first true Gen 2.2 soft IP core to support line rates of up to 6.25G in 1x/2x/4x lane widths. The IP solution consists of a highly flexible and optimized Serial RapidIO Physical Layer core, and a Logical (I/O) and Transport layer core. It is supported by 7 series and Virtex-6 FPGAs and comes with a configurable buffer design, reference clock module, reset module, and configuration fabric reference design.

Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP Features

  • 1x, 2x, and 4x Serial PHY – supports Kintex-7, Virtex-7, and Virtex-6 FPGAs
  • 1x, 2x and 4x Serial PHY – supports 1.25, 2.5, 3.125, 5.0, and 6.25 Gpbs line speed
  • Supports IDLE1 and IDLE2 sequence
  • Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
  • Support for 8/16 bit device IDs, programmable source ID on all outgoing packets
  • Support for priority based re-transmit suppression
  • Independently configurable 8/16/32 packet deep TX and RX buffer depths
  • AXI4-Stream interface for Data path and AXI4-Lite for the configuration Interface

Xilinx CPRI v4.1 LogiCORE IP
This core is designed to the Common Public Radio Interface (CPRI) standard specification v4.2. It is ideal for connectivity between Radio Equipment Controllers (REC) or baseband/channel cards and one or more Radio Equipment units (radio cards). The CPRI v4.1 LogiCORE IP is supported by 7 series FPGAs, and its optimized implementation supports radio I/Q data, radio unit management, and synchronization in a single efficient protocol.

CPRI v4.1 LogiCORE IP Features

  • Designed to CPRI Specification v4.2
  • Operates at line rates of 614.4 Mbps, 1228.8 Mbps, 2457.6 Mbps, 3.072 Mbps using Xilinx GTP transceivers
  • Operates at line rates of 614.4, 1228.8, 2457.6, 3072, 4915.2, and 6144 Mbps using Xilinx GTXE1 transceivers
  • Operates at line rates of 614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 9830.4 Mbps using Xilinx GTXE2 transceivers
  • Automatic speed negotiation
  • Configurable as master or slave
  • Suitable for use in both Radio Equipment, Controllers (RECs) and Radio Equipment (RE), including multi-hop systems
  • Supports 1 to 32 Antenna-Carriers per core
  • Available through the Xilinx CORE Generator

Xilinx JESD204B v.1.1 LogiCORE IP
This IP core overcomes I/O constraints and PCB layout cost and complexity by replacing wide parallel interface to data converters with 1/2/4 high speed serial interface links. It is the industry’s first soft IP core that is designed to Joint Electron Devices Engineering Council (JEDEC) JESD204B standard. The JESD204B v.1.1 LogiCORE IP core is supported by 7 series FPGAs, and can be configured as JESD204B Transmitter for interfacing to DAC device or JESD204B Receiver for interfacing to ADC device.

JESD204B v.1.1 LogiCORE IP Features

  • Designed to JEDEC JESD204B specification
  • Supports 1, 2, and 4 lane configurations
  • Supports scrambling and initial lane alignment
  • Supports 1-256 Octets per frame and 1-32 frames per multi-frame
  • Provides Physical and Data link layer functions
  • AXI4-Stream interface for data
  • AXI4-Lite for configuration interface
  • Delivered by CORE Generator software

More info: Xilinx