Xilinx (Nasdaq: XLNX) is teaming with Cadence Design Systems, Inc. (Nasdaq: CDNS), Mentor Graphics Corporation (Nasdaq: MENT), and Synopsys, Inc. (Nasdaq: SNPS) to address the challenges of ultra-high capacity FPGA design verification. The four companies will define and implement new verification flows to maximize productivity and quality of results for ultra high-density designs targeting today’s 65nm FPGAs as well as new and emerging FPGA architectures.
The collaboration will focus on expanding coverage, improving simulation runtime, and reducing verification time in an environment that allows designers to achieve aggressive design goals. Major releases of these tools and methodologies are expected in the first half of 2008.
Ongoing growth trends in FPGA architecture present escalating challenges for logic designers with increasing density points and capabilities across a wide range of application domains. Xilinx, Mentor, Synopsys, and Cadence will work together to build upon existing technologies to develop next-generation verification solutions, enabling system designers to streamline the verification process.