Xilinx has acquired AutoESL Design Technologies, which is a provider of high level synthesis for FPGAs and ASICs. AutoESL was founded in 2006 based on proprietary technology that was originally developed at UCLA. AutoPilot, AutoESL’s flagship high level synthesis tool, enhances productivity and speeds time-to-market for video, wireless, and high performance computing applications. The majority of AutoESL employees currently located in Cupertino, California and Beijing, China, will become Xilinx employees.
AutoESL’s high level synthesis will enable Xilinx to deliver the benefits of programmable platforms to a broader base of companies where system architects and hardware designers are accustomed to designing at a higher level of abstraction in C, C++ and System C. It will also enable Xilinx to address growing demand for tools that support electronic system-level (ESL) design methodologies for today’s complex designs targeted in field-programmable gate arrays (FPGAs).
AutoESL’s AutoPilot will increase designer productivity of Xilinx’s 6 series and 7 series of FPGA devices and new Extensible Processing Platform. The AutoPilot high level synthesis tool is optimized for Xilinx FPGA architectures and intelligently generates register transfer-level (RTL) code that produces the best possible QoR to meet throughput, power, area and timing design goals. It also reduces verification time by orders of magnitude due to the advantage of working at a higher level of abstraction in C, C++ or SystemC.
With high level synthesis, embedded engineers using Xilinx’s new Extensible Processing Platform will be able to more seamlessly partition designs between the ARM Cortex-A9 MPCore processor and the programmable logic. The combination of AutoPilot and ISE Design Suite will enable system architects, hardware designers and, embedded software developers (in the future) to apply a combination of serial and parallel processing to address the challenging system requirements presented by the global demand for embedded systems to perform increasingly complex functions.
Xilinx’s new Virtex-7 family of devices provides up to 2M logic cells and 4000 DSP48E1 slices. The combination of AutoPilot high level synthesis and plug-and-play IP will reduce development time for customers who model in C, C++ or SystemC. A new Xilinx-only version of AutoPilot will be available to designers in the first half of this year. AutoPilot will be available as an option for Xilinx’s ISE Design Suite software in the future.