TEK Microsystems Gemini-V6 FPGA-based Processing Solution

TEK Microsystems introduced the Gemini-V6 FPGA-based processing solution. The Gemini-V6 features two front end FPGA devices. One front end attaches to the ADCs and other front end attaches to the 4 GHz DAC. The front end FPGAs can be configured with Xilinx LX240, SX315, or SX475 devices. The TEK Gemini-V6 is a member of the QuiXilica family, and is based on the National Semiconductor ADC12D1800RF device. The Gemini-V6 will be available in January 2012.

TEK Microsystems Gemini-V6 FPGA-based processing solution

The Gemini-V6 includes two front end FPGA devices, one attached to the ADCs and one to the DAC. The front end FPGAs can be configured with LX240, SX315, or SX475 devices. If offers the highest FPGA processing density available in any 6U form factor and is the only VME / VXS platform that supports Virtex-6 FPGA devices. The two front end FPGAs are supplemented with a backend FPGA which can be used for additional processing or for backplane or front panel communications. The backend FPGA can also be configured with a range of Xilinx Virtex-6 FPGA options, from the standard LX240 up to a SX475, depending on application requirements.

The Gemini-V6 supports either one 12-bit analog-to-digital converter (ADC) input channel at 3.6 GSPS (Gigasamples per second) or three input channels at 1.8 GSPS, combined with a 12-bit DAC output channel operating at up to 4.0 GSPS. The Gemini-V6 is compatible with legacy VME systems and the newer ANSI/VITA 41 VXS based systems.

TEK Gemini-V6 Features

  • Based on the National Semiconductor ADC12D1800RF device
  • Two front end FPGA devices, one attached to the ADCs and one to the DAC
  • Front end FPGAs can be configured with LX240, SX315, or SX475 devices
  • Includes two ADC devices
  • Supports a total of either three channels plus trigger at 1.8 GSPS or one channels plus trigger at 3.6 GSPS, plus a separate 12-bit DAC output channel based on the Euvis M653D which operates at up to 4.0 GSPS
  • Sample-accurate trigger synchronization in all modes
  • Synchronization of input and output channels
  • Coherent processing for N-channel algorithms both within a single card and across multiple cards
  • GPS and timestamp inputs are available to support precise timing and geolocation
  • Six banks of DDR3 memory with total capacity of 5 GB and aggregate throughput of 32 GB/s
  • Backend FPGA has two banks of QDR-II memory available for applications that require memory with lower random access latency
  • Each FPGA supports a Gigabit Ethernet interface for control plane purposes
  • Onboard Gigabit Ethernet switch for network connectivity between the front panel, backplane interface, and all onboard FPGAs
  • Based on Tekmicro’s QuiXilica-V6 baseboard
  • Dedicated system management processor can be used to monitor power and thermal sensors
  • Includes QuiXstart technology, which supports FPGA bitstreams using either onboard flash memory or offboard network resources
  • Available for a wide range of operating environments, including commercial grade, rugged air and conduction cooled
TEK Gemini-V6 FPGA processing solution block diagram

More info: TEK Microsystems