Lattice XAUI / HiGig / HiGig+ to SPI4.2 Fabric Interface Chip
Lattice Semiconductor Corporation (NASDAQ: LSCC) introduced their XAUI/ HiGig(TM)/HiGig+(TM) to SPI4.2 programmable Fabric Interface Chip (FIC) solution for the LatticeSCM(TM) FPGAs. The solution provides a high-performance interface between the SERDES-based XAUI standard, used ubiquitously in 10G Ethernet networks, and SPI4.2, a very popular parallel bus interface used by Network Processor Unit (NPU) devices. When implemented in a LatticeSCM-15E FPGA packaged in a space-saving 256 fine pitch Ball Grid Array (fpBGA) package, the bridge solution requires a mere 17mm x 17mm on a printed circuit board while consuming only 2.5Watts of power, substantially less than competitive devices.
The Lattice solution uses the LatticeSCM device’s System Packet Interface Level 4 Phase 2 (SPI4.2) hard IP capability and includes Lattice’s 10Gigabit Ethernet Media Access Controller (MAC) soft IP core and the XAUI/HiGig/HiGig+ to SPI4.2 bridge design.
The solution is available as a XAUI to SPI4.2 IP bundle and can be downloaded from the Lattice site. Key features of the IP bundle include:
- Supports full-duplex bridging between NPUs (SPI4.2) and Ethernet Switches (XAUI//HiGig/HiGig+)
- Supports XAUI standard data rate of 3.125Gbps on the SERDES as well as the HiGig+ data rate (3.8Gbps maximum SERDES frequency offers ample design margin)
- Supports flow control in both directions
- Supports various burst sizes
- Marks all packets with errors received before transmitting
- Supports statistics collection from the MAC
List price of the complete bundle including the MAC, the bridge design and SPI4.2 core, along with documentation, is $14,950. An evaluation copy of the bundle is now available and can be downloaded by registered Lattice design tool users with up-to-date maintenance agreements without charge at Lattice Intellectual Property.
More info:
Lattice Unveils Lowest Power Programmable Fabric Interface Chip
Lattice Semiconductor
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