The FPE320, from VMETRO, is the industry’s first 3U VPX FPGA processing engine with support for the new FPGA Mezzanine Card (FMC/VITA 57) standard. The FPE320 incorporates the largest available Xilinx® Virtex®-5 FPGAs and an onboard FMC mezzanine site. The combination of high-performance FPGA processing and the flexibility of FMC-based I/O in a air- or conduction-cooled 3U VPX package is ideal for demanding real-time applications such as Electronic Warfare (EW) and Signal Intelligence (SIGINT), Electronic Counter Measures (ECM), and UAV sensor acquisition. The FPE320 is VPX (VITA 46) compliant with .8″ pitch and is available in both air and conduction cooled versions. It is expected to ship in Q4 2008.
VMETRO FPE320 FPGA Board Features
- Supports Xilinx Virtex-5 SXT, LXT and FXT FPGAs
- FMC (VITA 57) mezzanine site for I/O
- DDR2 SDRAM and QDRII SRAM memory resources
- Four x4 high-speed serial interconnects to the backplane for PCI Express, Aurora or Serial RapidIO
- Additional low-speed I/Os to the backplane
- FusionXF Development Kit for HDL development
- 3U VPX with .8″ Pitch
- Air and conduction cooled options
In 3U systems, physical board size has limited the use of large FPGAs with larger I/O mezzanines such as PMC/XMC. With the advent of the FMC I/O mezzanine standard, the largest available Virtex-5 FPGAs can be used in 3U systems because the I/O space requirements are minimized. The FPE320 supports Xilinx Virtex-5 SXT, LXT and FXT FPGAs in the FF1738 package and has a single FMC (VITA 57) mezzanine site for I/O. In addition, the FPE320 provides two banks of DDR2 SDRAM and two banks of QDRII SRAM memory along with four x4 high-speed serial interconnects (16 RocketIO[TM] GTPs) to the backplane for PCI Express®, Aurora[TM], or Serial RapidIO[TM] and additional user-defined I/Os to the backplane.
At the heart of the FPE320′s processing is a Xilinx Virtex-5 FF1738 package FPGA, the largest FPGA in the Virtex-5 family. FPGAs provide parallel processing capabilities that can be used to reduce processor count and system size. Operations such as FFTs, FIR filters and other fixed-point and/or repetitive processing tasks are highly suited for placement inside FPGAs. By providing a large FPGA node, processing tasks can tackle input from the FMC mezzanine site, backplane I/O or simply function as an adjunct processing resource to the general purpose processor in the system.
More information: FPE320 VPX Xilinx Virtex-5 FPGA Processor Board