Tokyo Electron Device inrevium TB-5V-LX110-DDR3 Evaluation Platform
The inrevium TB-5V-LX110-DDR3, from Tokyo Electron Device, is a Virtex-5 DDR3/LV-DDR2 SDRAM evaluation platform. The TB-5V-LX110-DDR3 is the first FPGA evaluation platform to include a DDR3 SODIMM (small outline dual in-line memory module) socket and is supplied with 1GByte DDR3 memory module. It can support DDR3 memory modules up to 4GByte. The inrevium TB-5V-LX110-DDR3 is ideal for ASIC/LSI prototyping that can be used to test DDR3 SDRAM with a maximum speed of 1,066Mbps and LV-DDR2 SDRAM with a maximum speed of 667Mbps. The new platform will be available in June 2009.
inrevium TB-5V-LX110-DDR3 Features
- FPGA: Xilinx XC5VLX110-3FFG1760C (XC5VLX330-2FFG1760C also available)
- PROM: Xilinx XCF128XFTG64C
- Memory: Elpida Memory DDR3 SDRAM: Chip (x 16-bit, 2pcs)
- LV-DDR2 SDRAM: Chip (x 32-bit, 1pc, 1.5V interface)
- LV-DDR2 SDRAM: Chip (x 16-bit, 1pc, 1.5V interface)
- DDR3 SDRAM: SO-DIMM socket (x 64-bit)
- 1Gbyte DDR3 SO-DIMM memory module is included
- Power supply: Linear Technology LTM4601EV#PBF, LTC3413EFE#PBF, etc
- Operating clock: 200MHz oscillator
- PLL-IC
- SAMTECH MMCX connector
- Type A connector for option boards: 2pcs
- Push-button switches, LEDs, DIP switches, General-purpose pin header
- Reference designs (Verilog HDL)
- DFI 2.0 compatible DDR3 SDRAM PHY reference design for Virtex-5
- Reference design incorporating a write leveling function with a validated maximum operating speed of 1066Mbps (available for purchase)
- Reference design with a validated maximum operating speed of 800Mbps
- DFI 1.0 compatible LV-DDR2 SDRAM PHY reference design for Virtex-5
- DVI frame buffer design using DDR3 chips
More information: Virtex-5 DDR3/LV-DDR2 SDRAM Evaluation Platform
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