Xilinx Stacked Silicon Interconnect Technology

Xilinx introduced stacked silicon interconnect technology that combines multiple FPGA die in a single package. With Xilinx’s stacked silicon interconnect technology, engineers can increase capacity, bandwidth and power savings for applications that require high-transistor and logic density, and high levels of computational and bandwidth performance. The technology enables designers to pack more FPGA resources (logic, memory, serial transceivers and processing elements) on a single FPGA device.

Xilinx stacked silicon interconnect technology

Xilinx Stacked Silicon Interconnect Highlights

  • Technology enables multiple FPGA die to be combined
  • More FPGA resources (logic, memory, serial transceivers and processing elements) on a single chip
  • 100x improvement in inter-die bandwidth per watt over conventional approaches
  • Does not consume high-speed serial or parallel I/O resources
  • Doubles the reach of the largest single-die FPGA devices
  • Ideal for applications such as next generation wired communications, high performance computing, and medical image processing
  • 28nm Virtex-7 LX2000T device will be the industry’s first multi-die FPGA
  • Data flows between a set of adjacent FPGA die across 10,000+ routing connections
  • Die sit adjacent to each other and interfaced to the ball-grid-array
  • Avoids the thermal flux and design tool flow issues of purely vertical die-stacking approaches
  • Ultra high-bandwidth, low-latency and low-power interconnect
  • Supported by ISE Design Suite 13.1
  • Ideal for the large-scale-integration of systems
  • Overcome the boundaries of Moore’s Law

More information: Xilinx