Aldec introduces Active-HDL 8.2 sp1, which is a RTL and gate-level simulator for FPGA design and verification engineers. Active-HDL 8.2 sp1 includes full support for Xilinx SecureIP, IEEE VHDL/Verilog encrypted IP, and an enhanced Assertions bundle option. Active-HDL is a Windows FPGA design and simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. Active-HDL 8.2 sp1 is available today.
The new Assertion bundle supports three Assertion types: IEEE 1800 SystemVerilog Assertions (SVA), Property Description Language (PSL), and Open Vera Assertions (OVA) for legacy designs. The bundle also supports a dedicated Assertions Viewer, Assertion debugging and complete visibility of Assertions, properties and Functional Coverage statements through the simulator.
Active-HDL includes an HDL Design tool suite, high-performance mixed-language simulator and a multi-vendor FPGA flow manager that controls Simulation, Synthesis and Implementation for Actel, Altera, Lattice, Quicklogic and Xilinx FPGAs and more than eighty popular EDA tools, in a single environment. Active-HDL supports Windows 7, Vista, XP and 2003, 32-bit and 64-bit operating systems.
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