Blue Pearl Software Suite now supports Synopsys’ Synplify Pro FPGA synthesis software for VHDL and SystemVerilog designs. Blue Pearl Software collaborated with Synopsys to create an optimized flow that works with Synplify Pro FPGA synthesis software. VHDL and SystemVerilog designers are now able to automatically generate an exhaustive set of constraints that address false and multi-cycle paths and that work with Synopsys’ synthesis flow.
Blue Pearl Software Suite’s connection to Synplify Pro software improves interoperability with Synopsys’ leading synthesis flow and makes it easier for FPGA designers to add Blue Pearl Software’s automatic Synopsys Design Constraints (SDC) generation to their flow. It offers users improved constraint analysis and a solution that minimizes design risks.
The Blue Pearl Software Suite for FPGA design with Synplify Pro is available now. Release 6.0 of the Blue Pearl Software Suite with capabilities that support FPGA designers was announced last month.
Blue Pearl Software Suite offers comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic Synopsys Design Constraints (SDC) generation for FPGA, ASIC and SOC designs. Its visualization and validation technology gives users immediate feedback for validating automatically generated pre-synthesis longest paths and SDC timing constraints.
More info: Blue Pearl Software, Inc.