Aldec, Inc. released Riviera-PRO 2008.02, which is a mixed language HDL simulator. Riviera-PRO 2008.02 now includes VHDL 2007, integrated SystemC 2.2 compiler and SystemVerilog DPI support. Riviera-PRO offers mixed language verification support for VHDL, Verilog®, SystemVerilog and SystemC for behavioral, structural and timing simulation of multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.02 is available today in three configurations; all licenses are floating and support UNIX®, Windows® and Linux® 32/64.
Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC, C/C++, Assertions and EDIF. Riviera-PRO works in command line mode for maximum speed or in state-of-the-art GUI for enhanced editing, tracing, and debugging capabilities, including code coverage and linting. Riviera-PRO is compatible with industry standards and interfaces with popular EDA products such as Synopsys® SmartModels(tm), LMTV(tm), Novas(tm), Denali®, MATLAB®, and Simulink®.
Riviera-PRO 2008.02 Highlights
- VHDL 2007 Support
Riviera-PRO 2008.02 supports many features of the VHDL standard draft (IEEE P1076-2007/D4.0), recently approved by Accellera. Constructs such as new data types, subprograms and operators, matching case statement, signal expressions in port maps and delimited comments are just some of the latest enhancements. The addition of these new VHDL constructs makes Riviera-PRO one the most advanced mixed language VHDL simulators on the market.
- SystemC 2.2
Riviera-PRO fully integrates the OSCI SystemC 2.2 compiler – the first version compliant with the IEEE Std 1666-2005 standard. The integrated debugging environment allows system level designers to run mixed simulation based on SystemC and HDL code from a common design environment. Code stepping and all break points, independent of SystemC/C++ or HDL, can be used to debug large SOC designs on Linux 32 and 64 bit platforms.
- New Capabilities
SystemVerilog DPI and classes support has been enhanced and the Denali® Memory Model interface now supports dedicated control commands in the console and simulation scripts from both VHDL and Verilog. The OVL library support has been upgraded to 2.1 and significant speed and compression improvements have been made to Aldec’s waveform viewer to provide more efficient debugging of large multi-million gate ASIC designs.
More info: Aldec Riviera-PRO