Lattice Semiconductor and Helion GmbH teamed on Intellectual Property (IP) cores for the video security and surveillance camera market. Helion’s IONOS video pipeline IP and Vesta evaluation platform targets the LatticeXP2, LatticeECP2M, and LatticeECP3 FPGA families. The Helion Vesta evaluation platform is a completely self-contained platform that enables the development and realization of image pipelines for camera systems, especially in tight form-factor video security applications such as network IP and dome cameras.
Helion IONOS Suite of IP Highlights
- 1080p60 Performance
- Supports full HD at 60 frames per second
- Supports up to 12MP sensors
- Offers seamless upgrade path and protects investment
- 1080p60 streaming data path through FPGA; no external frame buffer
- Offers quality at lower system cost
- Extremely Low latency
- Industry’s fastest Fast Auto Exposure
- Executes in 3 frames No visible display bloom or blackout; quick response to fast changing light
- 120dB scene dynamic range
- Maximum detail in both dark and light areas in a single image
- 192dB (32-bits) system dynamic range
- Exceeds the 150dB automotive manufacturer-specified requirements
- Wishbone compatible IP
- Easy to setup and use
- Comprehensive IP Suite
- End to end ISP solutions
Working with partner Helion, Lattice offers a comprehensive High Dynamic Range (HDR) pipeline that is fully configurable, works with industry standard HDR sensors, and delivers outstanding HDR performance in a FPGA based HDR implementation. Helion’s Vesta evaluation platform is a modular technology platform that combines a video processing baseboard, an image sensor and a Lattice FPGA capable of supporting a range of Helion’s IONOS video pipelines.
Helion offers a comprehensive selection of video pipelines, ranging from basic to advanced monochrome and color pipelines, all the way through high resolution advanced High Dynamic Range Imaging (HDRI) color pipelines. Depending on the pipeline selected, it will consist of a number of individual video processing IP cores, such as defective pixel correction, logic-efficient 3 x 3 De-Bayering, high quality 5 x 5 De-Bayering, color-correction matrix, gamma correction, auto-exposure, auto-white balance and more. These cores also support Lattice FPGA devices, and all are compatible and simply connected using the Wishbone bus.