MathWorks introduced HDL Coder and HDL Verifier. HDL Coder automatically generates HDL code from MATLAB and helps engineers implement FPGA and ASIC designs from the MATLAB language. HDL Verifier features FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. HDL Coder and HDL Verifier are available now. Pricing for HDL Verifier starts at $3,250 and pricing for HDL Coder starts at $10,000. With HDL Verifier and HDL Coder, MathWorks now provides HDL code generation and verification across their MATLAB and Simulink tools.
HDL Coder generates portable, synthesizable VHDL and Verilog code from MATLAB functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design. As a result, engineering teams can now identify the best algorithm for hardware implementation. Traceability between Simulink models and generated HDL code also supports the development of high-integrity applications that adhere to DO-254 and other standards.
HDL Coder Features
- Target-independent, synthesizable VHDL and Verilog code
- Code generation support for MATLAB functions, System objects, and Simulink blocks
- Mealy and Moore finite-state machines and control logic implementations using Stateflow
- Workflow advisor for programming Xilinx and Altera application boards
- Resource sharing and retiming for area-speed tradeoffs
- Code-to-model and model-to-code traceability for DO-254
- Legacy code integration
HDL Verifier now supports FPGA hardware-in-the-loop verification for Altera and Xilinx FPGA boards. HDL Verifier provides co-simulation interfaces that link MATLAB and Simulink with Cadence Incisive, Mentor Graphics ModelSim, and Questa HDL simulators. With these capabilities, engineers can rapidly verify that their HDL implementation matches their MATLAB algorithms and Simulink system specifications.
HDL Verifier Features
- Co-simulation support for Cadence Incisive and for Mentor Graphics ModelSim and Questa
- FPGA-in-the-loop verification using Xilinx and Altera FPGA boards
- MATLAB functions and Simulink blocks
- Generation of IEEE 1666 SystemC TLM 2.0 compatible transaction-level models
- Interactive or batch-mode cosimulation and debugging
- Single-machine, multiple-machine, and cross-network cosimulation
More info: MathWorks