Aldec Releases Riviera-PRO 2012.02 for FPGA and ASIC Verification

Aldec released version 2012.02 of their Riviera-PRO. The latest version of the mixed-language verification tool supports a number of advanced verification methodologies that will benefit the designers of complex FPGAs and those migrating to ASIC. Riviera-PRO v2012.02 supports the verification environments constructed with the Universal Verification Methodology (UVM) class library and new SystemVerilog IEEE 1800-2009 and VHDL IEEE 1076-2008 constructs. This makes Riviera-PRO an ideal platform for working with the Open Source VHDL Verification Methodology (OS-VVM).

With the new version of Riviera-PRO, it is now possible to log class objects and display them in Riviera-PRO’s Waveform Viewer. This feature makes possible the analysis of dynamic objects over time, organically combined with the objects of any other data type. It is also possible to log information, warning and error messages, generated during simulation runtime in conjunction with appropriate markers displayed directly in the Waveform.

Riviera-PRO 2012.02 ships with UVM 1.1a , which is the latest version of the industry-standard SystemVerilog-based verification library. The latest version of Riviera-PRO includes multi-threaded SystemVerilog compilation (which is circa 25% faster on a typical UVM-based testbench), reduced compiler noise (to ensure clean and concise logs) and new environment variables that facilitate the use of the UVM library itself and make scripting much easier. Riviera-PRO 2012.02 also features enhancements to the tool’s HDL Editor and Waveform Viewer. The Aldec tool is a versatile script-based, design, (common-kernel) simulation, analysis and debug environment for FPGA and ASIC designers.

Riviera-PRO v2012.02 enables a number of new constructs. Such as:

  • SystemVerilog
    Constructs such as forward typedef, extern module declarations and dynamic arrays in constraint blocks
  • SystemVerilog Assertions (SVA)
    Constructs such as multi-clocked properties and sequences, so a great benefit to engineers working on multiple clock domain designs
  • VHDL
    Constructs such as the ‘force’ and ‘release’ signal assignment statements

More info: Aldec Riviera-PRO 2012.02 (pdf)