CAST introduced the UDPIP IP core. The CAST UDPIP is a hardware implementation of the User Datagram Protocol (UDP), which is a fast, simple, transport layer protocol that works without the handshaking and error correction of the more rigorous Transmission Control Protocol (TCP). The UDPIP IP core is available now in Verilog or as an optimized netlist for Altera and Xilinx FPGAs. Integration with MAC cores from CAST, FPGA vendors, or other sources is available. Integration with CAST compression cores (e.g., the H.264 encoder) is also available.

CAST UDPIP IP core for implementing User Datagram Protocol (UDP) transport layer stack

The CAST UDPIP core can operate without need for a processor and can handle any likely UDP and streaming media requirements. The core transmits and receives UDP packet data messages to one (unicast) or more (broadcast) targets on an Ethernet LAN, using IPv4 without packet fragmentation (DHCP support is optional). It generates and validates outgoing and incoming checksums; Ethernet CRC error correction is an option.

The UDPIP core form CAST supports a superset of typical UDP/IP functions and is configurable for transmit, receive, or both (full-duplex). The IP core works with any 10/100/1000 Mbit Ethernet MAC transceiver, including FPGA MACs from Altera and Xilinx and synthesizable versions such as the CAST MAC-1G core. Integrating the core in system-on-chip designs is made easier through support for industry-standard streaming and bus interfaces.

Silicon implementation results indicate this is one of the smallest available such cores. For example, it uses just 1000 slices for the receive function on a Xilinx Virtex-5 device. In addition, performance suitable for 10 gigabit Ethernet (10GbE) has been achieved in some ASIC implementations.

CAST UDPIP Core Features

  • 10/100/1000 Ethernet support
  • 10 Gbit Ethernet (10GbE) support
  • IPv4 support without packet fragmentation
  • Transmit and receive
  • ARP with cache
  • ICMP (ping reply)
  • UDP/IP unicast or broadcast
  • UDP port filtering
  • UDP/IP checksums generation and validation, and optional Ethernet CRC validation
  • Ethernet framing processing for non-UDP user-provided packets
  • Optional DHCP client
  • Run time programmable network parameters:
    • Local, destination and gateway IP address
    • Source and destination UDP ports
    • MAC address
  • ARP for smooth operation in multiple-access networks
  • Ping support for testing network connectivity
  • Flexible packet data interface:
    • 8- to 16-bits wide streaming capable using either AMBA AXI4-Stream or Avalon-ST
    • Optional 32-bits wide AHB, AXI, Avalon-MM or Wishbone SoC buses
  • eMAC-independent; works with CAST, FPGA vendor, or third-party MACs
  • Separate clock domains for packet processing and control/data interfaces
  • Configurable buffer sizes
  • Rich interrupt support for system events
  • Available pre-integrated with CAST, Altera, Xilinx, or other third-party eMAC core, and media codec cores like the CAST H.264 Video Encoder

More info: CAST