Xilinx has taped out the semiconductor industry’s first 20nm device, and the PLD industry’s first 20nm All Programmable device. In addition, Xilinx has also implemented the industry’s first ASIC-class programmable architecture called UltraScale. According to Xilinx, the company is about a year ahead in delivering 1.5–2X more realizeable system-level performance and integration.
The UltraScale architecture was developed to scale from 20nm planar, through 16nm and beyond FinFET technologies, and from monolithic through 3D ICs. It not only addresses the limitations to scalability of total system throughput and latency, but directly attacks the number one bottleneck to chip performance at advanced nodes: the interconnect.
Xilinx UltraScale Architecture Features
- Massive data flow optimized for wide buses that support multi-terabit throughput
- Multi-region ASIC-like clocking, power management, and next generation security
- Highly optimized critical paths and built-in high-speed memory, cascading to remove bottlenecks in DSP and packet processing
- Step function in inter-die bandwidth for 2nd generation 3D IC systems integration
- Massive I/O and memory bandwidth with dramatic latency reduction and 3D IC wide memory-optimized interface
- Elimination of routing congestion and co-optimization with Vivado tools for >90% device utilization without degradation in performance
Xilinx has worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The 28nm collaboration resulted in the industry’s first 28nm tape-out and the industry’s first All Programmable FPGA, SoC, and 3D IC devices. According to the company, it is a generation ahead in price/performance/watt, programmable systems integration, and BOM cost reduction.
Vivado Design Suite early access supporting UltraScale architecture-based FPGAs is now available. Initial UltraScale devices will be available in the fourth quarter of calendar year 2013.
More info: Xilinx UltraScale Architecture (pdf)