Altera revealed plans for their next generation of 20nm products. According to the company, they will offer a system-integration platform that combines the hardware programmability of FPGAs with the software flexibility of digital signal processors and microprocessors along with the efficiencies of application-specific hard intellectual property (IP). Altera’s next-generation devices leverage TSMC’s 20nm process technology. 20nm system-on-chip (SoC) FPGAs provide engineers a software migration path from 28nm to 20nm while delivering a 50% processor subsystem performance increase.
Altera’s 20nm mixed-system fabric includes the integration of 40-Gbps transceiver technology, a next-generation variable-precision digital signal processing (DSP) block architecture that delivers over 5 TFLOPs of IEEE 754 floating-point performance, and heterogeneous 3D ICs that integrate FPGAs with a user-customizable HardCopy ASIC or a variety of other technologies, including memory, third-party ASICs and optical interfaces through an innovative high-speed interface.
The 20nm mixed-system fabric also offers continued innovations in power management, including adaptive voltage scaling, Programmable Power Technology, and optimized process technology, which enable Altera to reduce device power consumption up to 60% compared to its previous generation of devices.
Altera Next Generation 20nm Products
Highest Serial Bandwidth: 40-Gbps Chip-to-Chip and 28-Gbps Backplane Transceivers
Innovations made to Altera’s transceiver technology at 20nm deliver the industry’s highest serial bandwidth, enabling the migration to 100G backplane and 400G systems. The 20nm devices will include both 28-Gbps transceivers to drive CEI-25G-LR, Ethernet 4x25G backplanes and 40-Gbps transceivers designed to interface with chip-to-chip or chip-to-optical modules. The transceiver technology innovations Altera is making at 20nm provide the foundation for developing CEI-56G-compliant transceivers that offer the connectivity to drive the next generation of 400G optical networks, 400G line cards and beyond.
Heterogeneous 3D ICs Featuring a High-Speed Chip-to-Chip Interface
At 20nm, Altera will introduce an innovative high-speed chip-to-chip interface that integrates multiple dies together in a 3D package. This interface enables Altera to deliver customer-specific heterogeneous 3D systems that mix FPGAs with a user-customizable HardCopy ASIC, or a variety of other technologies, including memory, third-party ASICs and optical interfaces. Integrating FPGAs with HardCopy ASICs or third-party ASICs makes it possible for Altera to deliver single-device solutions that offer 10X higher system integration versus any 28nm product. Altera’s heterogeneous 3D ICs will be manufactured using TSMC’s chip-on-wafer-on-substrate (CoWoS) process. The devices will enable developers to increase system integration, system performance and product differentiation while reducing system power, board space and costs.
Industry’s Highest DSP Performance with Highest TFLOPs/Watt
Altera is resetting industry benchmarks in TFLOPs/watt with 20-nm devices. Enhancements made to its next-generation variable-precision DSP block deliver over 5 TFLOPs of IEEE 754 floating-point performance. At these levels, Altera’s 20nm devices deliver over 5X higher TFLOPs per watt versus competitive FPGAs. Combining the productivity benefits of an OpenCL C-based design flow, an ARM hard processor subsystem and the highest TFLOPs/watt silicon efficiency, Altera’s 20nm devices provide the ultimate heterogeneous computing platform.
More info: Altera Corporation