Lattice PCI Express 2.0 Solution

According to Lattice Semiconductor, their solution is interoperable with existing PCIe 2.0 supported systems. At a recent PCI-SIG workshop, the LatticeECP3 FPGA and its PCI Express (PCIe) IP core passed PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations. As a result, the LatticeECP3 FPGA family is now compliant with the PCI Express 2.0 specification at 2.5Gbps. Lattice also worked with Trellisys on a PCIe Bus Functional Model (BFM) for Lattice’s PCI Express x1 and x4 IP Cores.

Lattice PCI Express 2.0 Solution

  • Enables engineers to use a low cost FPGA in PCIe v2.0 compliant systems
  • Interoperable with existing PCIe 2.0 supported systems
  • Reduces cost and power
  • High reliability for 2.5Gbps PCIe v2.0 systems
  • Ideal for communications, multimedia, server and mobile platforms
  • Lattice PCI Express IP Suite is currently priced at $99 for a limited time ($995 after promotion)

Trellisys PCIe Bus Functional Model

  • Robust and cost-effective PCIe BFM for Lattice’s PCI Express x1 and x4 IP Cores
  • PCIe BFM focuses on the transaction layer (typically where application logic is implemented)
  • Approach assumes that physical and data link layers have already been verified by Lattice
  • Supports both Verilog and VHDL
  • Verified on both the Aldec Active-HDL and Riviera-PRO simulators
  • Delivered as precompiled code
  • Includes procedural library that an advanced verification suite can be based
  • Designers can use the IPexpress tool within the Lattice Diamond design tool suite
  • IPexpress tool includes the PCIe core, reference designs, scripts, BFM and simulation models
  • Reduces design complexity and decreases the time to market window for PCI Express designs

More info: Lattice Semiconductor | Trellisys