Tensilica TRAX-PC Processor Trace

Posted by Ken Cheung in Tool on Monday, December 10, 2007
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« Xilinx Virtex-4 FPGAs Speed SGI Altix

Tensilica®, Inc. added an optional full-speed, non-intrusive instruction trace capability to its configurable processor cores. Tensilica’s TRAX-PC processor trace capture macrocell is Nexus 5001 compatible and ideal for debugging complex, challenging real-time applications such as engine and motor control. Software control and use of the on-chip TRAX hardware is fully integrated into Tensilica’s Xplorer(TM) integrated design environment (IDE) so software engineers can easily develop and debug programs while using the TRAX-PC trace macrocell.

Tensilica’s TRAX-PC processor trace capture block is an optional item for use with all Diamond Standard and Xtensa processors. It provides tracing information through an SoC’s JTAG debug port without requiring added device pins. It helps designers trace all changes in program flow including exceptions and interrupts. The trace block uses a circular on-chip trace buffer with user-defined sizing to capture the trace stream and accepts PC-based triggers and external trigger inputs.

Tensilica’s associated software tools convert the compressed trace into an annotated program disassembly for easy debugging. These tools are fully integrated into Tensilica’s world-class Eclipse-based, Xtensa Xplorer(TM) integrated design environment (IDE). The Xplorer IDE provides a powerful visualization and debugging environment to both develop and debug programs using the TRAX-PC trace macrocell.

The TRAX-PC processor trade capture macrocell is available now for use with all current Tensilica processor products.

More info: Tensilica

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