White Paper: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs

Xilinx recently published a white paper about floating-point DSP algorithms. According to the technical paper, Xilinx System Generator for DSP enables the creation of custom precision datapaths for optimal area and power. The floating-point design flow generates an implementation that is bit- and cycle-accurate to the original simulation model. The title of the white paper is: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs. It was written by Tim Vanevenhoven.

Floating-point arithmetic, long the realm of general-purpose CPUs, DSPs, and graphics processing units (GPUs) is seeing growing use in FPGAs. This trend is driven by a host of new applications in medical imaging, wireless, and defense that require large dynamic range as well as by a strong need to simplify the design process.

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Up until recently, most algorithms implemented in FPGAs were fixed-point. Current trends in system requirements and available FPGAs are causing floating-point implementations to become more common. The IEEE 754 standard specifies data types that are sufficient for fixed-architecture processors but limit the flexibility available in FPGAs. Using only these data types unnecessarily restricts designers from optimizing their floating-point FPGA implementation.

The high-level floating-point design flow available today with System Generator provides users a powerful environment that allows the creation of custom precision datapaths for optimal area and power. Unlike alternative FPGA design flows, the floating-point design flow also generates an implementation that is bit- and cycle-accurate to the original simulation model.

More info: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs (pdf)