Webinar: How to Quickly Design a Low-Cost ASIC

NEC and Tensilica are sponsoring a webinar on how to quickly design low-cost custom logic. The webcast will take place on Thursday, December 6th at 11 am Pacific (2:00 pm Eastern). The seminar will focus on designing low-cost ASICs using synthesizable 200-megahertz (MHz) 32-bit controllers.

The event will cover:

  • Trade-offs between various implementation technologies from a power and performance perspective
  • How gate array technology compares with FPGAs and custom ASICs across a number of design requirements
  • Critical factors you need to know if you’re considering moving from an 8- or 16-bit up to a 32-bit embedded controller core
  • Why larger is not necessarily better when it comes to choosing embedded controller cores

For attendees located in the Americas, NEC Electronics America will waive the license fee for the Tensilica Diamond 106Micro designed in an NEC gate array (from $25,000 to $75,000 value). The small, low-power Diamond Standard 106Micro core is designed for simple 32-bit controller applications in system-on-chip (SoC) designs, and is available directly from NEC Electronics America. Participants in the seminar will also be able to download a free Tensilica software development tool kit for 15-day use.

More info: How to Quickly Design a Low-Cost ASIC