Tokyo Electron Device V-by-One HS IP Core for Xilinx FPGA Spartan-6
Tokyo Electron Device (TED) introduced the V-by-One HS IP Core for Xilinx FPGA Spartan-6. V-by-One HS is an open standard for allowing transmission of large amounts of video and control data to support the higher frame rates and the higher resolutions required by next-generation flat-panel displays. It enables high-speed serial data transfer technology capable of variable transfer speeds beyond 3Gbps, thus requiring far fewer channels for transferring data. The V-by-One HS video interface standard was developed by THine Electronics.
V-by-One HS IP Core Features
- Up to 3.75Gbps data rate per lane on Virtex-6 (up to 3.125Gbps on Spartan-6)
- Targets a high speed video signal transmittion based on internal connection of the equipment
- Data scrambling and Clock Data Recovery (CDR) to reduce EMI
- CDR solves the skew problem between clock and data at conventional transfer system
- 1, 2, 4, and 8 lanes operation (Design service for 16 and 32 lanes are available)
- Variable settings of driver swing, pre-emphasis and equalizer
- Flexible implementation and package compatibility
More info: Tokyo Electron Device | Xilinx | THine Electronics
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