Tokyo Electron Device MECHATROLINK-III IP Core for Xilinx Spartan-6 FPGA
Tokyo Electron Device has developed an IP core compatible with the MECHATROLINK-III standard for implementation with the low-cost Xilinx Spartan-6 FPGA family. The MECHATROLINK-III specification is an open motion field network communications standard established by the Iruma, Saitama Prefecture, Japan-based MECHATROLINK Members Association. Tokyo Electron Device’s MECHATROLINK-III compliant IP core for Spartan-6 FPGAs will be available in the third quarter of this year.
Tokyo Electron Device MECHATROLINK-III Master/Slave IP Core Features
- User-selectable : Master/Slave
- CPU built-in FPGA is intelligent function
- Connet CPU: 16bit, 8bit
- Connect FPGA internal resource, asynchronous bus
- Max 66MHz Clock, High-speed, synchronous buss as PCI Express in the connection, it is possible to connect it without decreasing throughput
- MECHATROLINK-III Network x 2 Port (For MII interface 100Mbps Full Duplex mode)
- 32-bit Joint memory interface / 32-bit register interface
- 2 interrupt outputs
- Little Endian
The IP core supplied by Tokyo Electron Device is compliant with the MECHATROLINK-III standard. It supports a data transfer speed of 100Mbps, cycle time of 31.25microns-64ms, and capable of connecting up to 62 equipment nodes, the control of which can be fully synchronized. Use of the IP core enables separate master and slave functions if required. This solution makes the system more compact, faster, and highly integrated, and reduces system costs compared with using ASICs.
MECHATROLINK is an open network communication system for motion control. It connects the components of factory automation (FA) systems (such as servo motors, inverters, and stepping motors) with a controller.
More info: Xilinx | Tokyo Electron Device | MECHATROLINK
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