Tag Archives: Zynq

Barco Silex Debuts Multi-channel Video over IP with JPEG 2000 Reference Design

Barco Silex multi-channel Video over IP with JPEG 2000 reference design

Barco Silex released the multi-channel Video over IP with JPEG 2000 reference design. The VoIP reference design integrates the BarcoSilex JPEG 2000 Encoder and Decoder IP Cores, the Barco Silex high-performance memory controller core, and the Xilinx SMPTE 2022-1/2 and Ethernet MAC LogiCORE IP Cores for Xilinx 7 Series FPGAs and Zynq All Programmable SoC.

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Webinar: Designing Advanced Embedded Systems with Xilinx Zynq

Techonline is offering a webinar this week about the Xilinx Zynq. The title of the webcast is Designing Advanced Embedded Systems with Xilinx Zynq: How to Break Software Bottlenecks with Accelerators. The online seminar will take place Thursday, September 5, 2013 at 11am PST (2pm EST, 6pm GMT). The webinar will be presented by Barrie Mullins (Zynq Development Director, Xilinx) and Rob Armstrong Jr.(Processor Specialist FAE, Xilinx).

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Alpha Data ADM-XRC-7Z1 XMC Mezzanine Card Features Xilinx Zynq SoC

Alpha Data ADM-XRC-7Z1 XMC Mezzanine card

Alpha Data introduced their ADM-XRC-7Z1 XMC Mezzanine card. The ADM-XRC-7Z1 features the Xilinx Zynq System-on-Chip (SoC). The ADM-XRC-7Z1 ships with a Software Development Kit (SDK), which includes example designs and software drivers. The board is available in industrial grade and air or conduction cooled variants. The ADM-XRC-7Z1 XMC Mezzanine card suitable for initial development through to deployment in rugged environments.

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RONETIX Power Embedded Debug Interface Supports Xilinx Zynq

Ronetix’s power embedded debug interface (PEEDI) now supports the Xilinx Zynq family. This is in addition to support for ARM, Cortex, XScale, ColdFire, Blackfin, MIPS32 and AVR32. The new support helps engineers with Flash programming and high speed GNU gdb debugging. The Ronetix PEEDI with support for Xilinx Zynq family is available now.

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