Tag Archives: Xilinx

Reflex CES Introduces Aurora-like 64B/66B IP Core

Reflex CES FPGA Aurora-like 64B/66B IP core

Reflex CES introduced their FPGA Aurora-like 64B/66B IP core. The new IP assures interoperability between all leading FPGAs, whatever the performance of their backplanes and systems, from 1 to 14Gbps, and whatever the generic or configurable features incorporated. The Reflex CES Aurora-like 64B/66B IP Cores are available with encrypted or VHDL source code license agreements, encrypted test-benches, reference designs and a user guide.

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Analog Devices Announces JESD204B Xilinx Transceiver Debug Tool

Analog Devices JESD204B Xilinx Transceiver Debug Tool

Analog Devices recently launched the JESD204B Xilinx Transceiver Debug Tool. The FPGA-based reference design with software and HDL code reduces the design risk of high-speed systems incorporating JESD204B-compatible converters. It supports the 312.5-Mbps to 12.5-Gbps JESD204B data converter-to-FPGA serial data interface and Xilinx Inc., 7 series FPGAs and Zynq-7000 All Programmable SoCs.

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Xilinx Introduces Virtex-7 FPGA VC709 Connectivity Kit

Xilinx Virtex-7 FPGA VC709 Connectivity Kit

Xilinx introduced their Virtex-7 FPGA VC709 Connectivity Kit. The tool is a 40 Gbps platform that enables designers to accelerate design productivity for high-bandwidth and high-performance applications, such as network interface cards for security, network monitoring, and high frequency trading appliances. The Virtex-7 FPGA VC709 Connectivity Kit is available now for shipping. It is priced at $4,995.

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Xilinx JESD204 LogiCORE IP Achieves Interoperability with ADI AD9250

Xilinx and Analog Devices have achieved JESD204B interoperability between Xilinx JESD204 LogiCORE IP in the Kintex-7 FPGA and the ADI AD9250 analog-to-digital high-speed data converter. The results confirm that off-the-shelf ADI JESD204B data converters and Xilinx FPGAs work together seamlessly. The interoperability means manufacturers can take advantage of JESD204B to accelerate time-to-market for their new products by shortening development time, reducing system test effort, and minimizing development issues.

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Barco Silex Debuts Multi-channel Video over IP with JPEG 2000 Reference Design

Barco Silex multi-channel Video over IP with JPEG 2000 reference design

Barco Silex released the multi-channel Video over IP with JPEG 2000 reference design. The VoIP reference design integrates the BarcoSilex JPEG 2000 Encoder and Decoder IP Cores, the Barco Silex high-performance memory controller core, and the Xilinx SMPTE 2022-1/2 and Ethernet MAC LogiCORE IP Cores for Xilinx 7 Series FPGAs and Zynq All Programmable SoC.

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Analog Devices Design Conference to Cover Xilinx All Programmable FPGA

Analog Devices, Xilinx, MathWorks and Avnet Electronics Marketing are teaming together at the ADI Design Conference. The virtual event will give analog, mixed-signal and embedded systems engineers the opportunity to learn from leading, high-performance signal processing industry experts. The online conference will take place from 12 pm to 5 pm EDT with a live keynote speaker and interactive Q&A sessions.

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Xilinx All Programmable Abstractions Improves Productivity

Xilinx All Programmable Abstractions

Xilinx introduced their All Programmable Abstractions initiative. Xilinx All Programmable Abstractions improve productivity of hardware designers and help systems and software developers to directly leverage All Programmable FPGA, SoCs, and 3D ICs. Xilinx and its ecosystem Alliance members now support a combination of software, model, platform, and IP-based design environments.

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Webinar: Designing Advanced Embedded Systems with Xilinx Zynq

Techonline is offering a webinar this week about the Xilinx Zynq. The title of the webcast is Designing Advanced Embedded Systems with Xilinx Zynq: How to Break Software Bottlenecks with Accelerators. The online seminar will take place Thursday, September 5, 2013 at 11am PST (2pm EST, 6pm GMT). The webinar will be presented by Barrie Mullins (Zynq Development Director, Xilinx) and Rob Armstrong Jr.(Processor Specialist FAE, Xilinx).

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Webinar: Accelerating OpenCV with Zynq-7000, Vivado HLS Video Libraries

Xilinx is hosting a webinar about the Vivado HLS Video Libraries. The webcast will show how to rapidly accelerate real-time computer vision algorithms and integrate them into designs using Xilinx Zynq-7000 All Programmable SoC devices. The title of the webinar is: How to Accelerate OpenCV Applications with Zynq-7000 All Programmable SoC using Vivado HLS Video Libraries. The online seminar will take place Wednesday, August 28, 2013 at 8am PST (11am EST, 3 GMT).

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Enclustra Mars ZX3 Embedded Processing Module Features Xilinx Artix-7 FPGA

Enclustra Mars ZX3 embedded processing module (EPM)

Enclustra’s Mars ZX3 embedded processing module is based on the Xilinx Zynq-7020 Extensible Processing Platform. The Mars ZX3 EPM provides a complete system solution in an industry-standard SO-DIMM form factor (68 x 30 mm). The ZX3 is the third member of the Mars family of SO-DIMM sized FPGA modules. The first members included the Mars MX1 and Mars MX2 based on the Artix-7 family of Xilinx FPGA’s. All Mars modules share a common pinout (with some restrictions) which enables easy migration.

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