Altera, Arrow Electronics, and MathWorks are hosting the DSP Forum. The event will discuss application-specific digital signal processing design methodologies targeted for Altera FPGAs. DSP Forum will also explain how the combination of DSP Builder’s model-based design flow and MathWorks tools helps implement high-performance floating-point DSP. The one-day event will take place in multiple cities from May 1st to June 7th.
Xilinx recently introduced the Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE, CPRI v4.1 LogiCORE, and JESD204B v.1.1 LogiCORE IP cores. The Xilinx three LogiCORE IP cores support connectivity standards and will help developers address design challenges in building new wireless equipment with higher system capacities. The Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP, JESD204 v1.1 LogiCORE IP , and CPRI v4.1 LogiCORE IP are ideal for building programmable, flexible and cost effective 3G+/4G wireless base stations. They are available in Xilinx’s ISE Design Suite 13.3 and can be evaluated free of charge.
Altera introduced their RapidIO MegaCore Function IP core. It is implemented in a Stratix IV GX FPGA with a Serial RapidIO Gen 2 switch from Integrated Device Technology (IDT). The IP core is the first Serial RapidIO Gen2 FPGA-based solution. The RapidIO MegaCore Function IP core is available now for download. It is available as encrypted IP or as source code for complete user control.
During National Instruments NIWeek 2010, Xilinx will offer demonstrations and technical sessions based on the LabVIEW FPGA Module. The sessions will focus on aerospace, industrial, medical and wireless applications. Xilinx will also show how their rad-hard Virtex-5QV FPGA is ideal for space applications. NIWeek 2010 will take place August 3-5 at the Austin, Texas Convention Center. The event focuses on graphical system design.
Analog Devices (ADI) and Xilinx announced the MS-DPD (mixed-signal, digital pre-distortion) development platform. MS-DPD helps multi-carrier cellular base station manufacturers reduce engineering resources and improve time to market. Xilinx’s Virtex-6 FPGA ML605 (field-programmable gate array) Evaluation Kit connects to the MS-DPD board through an industry-standard VITA-57 FMC connector. Using this system, the FPGA can be used to implement required radio algorithms leveraging the ADI signal chain available on the MS-DPD. The ADI MS-DPD development boards are available now for $3,995 each.
CoWare announced the 2010.1 release of CoWare SPW products. The SPW 2010.1 release advances the LTE (Long Term Evolution) Wireless Reference Library and adds a complete Xilinx implementation flow that includes direct source translation technology from C Data Flow (CDF) into RTL. The CoWare SPW 2010.1 release is available immediately. With this release, CoWare has reverted back to the product’s original SPW name (previously Signal Processing Designer, SPD).