Tag Archives: White Paper

White Paper: Delivering the Right Power and Performance for 28nm High-End FPGAs

Updated 100GbE OTU4 Transponder Power Comparison Using L Devices ~ Altera

Altera published a white paper that explores how their innovations in power and performance continue to enable designers to create differentiating high-performance systems for their end customers. The article outlines the steps taken from process selection through tools and modeling to ensure that the high performance was supported with a competitive power footprint. The title of the Altera technical paper is Delivering the Right Power and Performance for 28nm High-End FPGAs.

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White Paper: Real-Time Challenges and Opportunities in SoCs

Real-Time Challenges and Opportunities in SoCs White Paper

Altera published a white paper that explores an advanced motor drive or inverter application to illustrate how silicon convergence affects real-time design. The technical paper explains how FPGA and SoC devices speed silicon convergence. The latest advancement in SoC integrates an Altera FPGA with an ARM applications processor, plus a rich peripheral processor subsystem. The title of the Altera article is Real-Time Challenges and Opportunities in SoCs.

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White Paper: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs

Xilinx recently published a white paper about floating-point DSP algorithms. According to the technical paper, Xilinx System Generator for DSP enables the creation of custom precision datapaths for optimal area and power. The floating-point design flow generates an implementation that is bit- and cycle-accurate to the original simulation model. The title of the white paper is: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs. It was written by Tim Vanevenhoven.

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White Paper: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs

Altera published a white paper about how Altera FPGA devices are addressing 100-GbE line card design challenges. As various standard bodies finalize the 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want to design 100G production systems. As a result of increasing demand for more bandwidth, service providers are looking at emerging 40-GbE/100-GbE standards for their next-generation line card options. Altera Stratix V FPGAs solve the bandwidth problem by providing integrated 12.5-Gbps transceivers with hardened 100G PCS functions on the 28nm technology node.

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White Paper: Using Multi-Gigabit Transceivers to Test and Debug FPGA

Byte Paradigm recently published a white paper about testing and debugging a FPGA with multi-gigabit transceiver. The technical paper features Byte Paradigm’s new Thunder Series probe. The PC-based instrument uses FPGA multi-gigabit transceivers as high-speed interface for collecting trace data and inserting test pattern stimulus during FPGA testing and debugging. The article discusses the advantages of using high bandwidth links in combination with adequate embedded instrumentation IP implemented in FPGA.

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