MSC and eVision Systems will be hosting Lattice FPGA workshops next month. The one-day events will focus on FPGA design with VHDL using MachXO2 devices from Lattice Semiconductor. The workshops are held in German language with English slides. The workshop costs 129€ per person plus VAT. The training includes a MachXO2 Breakout Board and Lattice SW starter kit.
Blue Pearl Software Suite now supports Synopsys’ Synplify Pro FPGA synthesis software for VHDL and SystemVerilog designs. Blue Pearl Software collaborated with Synopsys to create an optimized flow that works with Synplify Pro FPGA synthesis software. VHDL and SystemVerilog designers are now able to automatically generate an exhaustive set of constraints that address false and multi-cycle paths and that work with Synopsys’ synthesis flow.
Aldec released version 2012.02 of their Riviera-PRO. The latest version of the mixed-language verification tool supports a number of advanced verification methodologies that will benefit the designers of complex FPGAs and those migrating to ASIC. Riviera-PRO v2012.02 supports the verification environments constructed with the Universal Verification Methodology (UVM) class library and new SystemVerilog IEEE 1800-2009 and VHDL IEEE 1076-2008 constructs. This makes Riviera-PRO an ideal platform for working with the Open Source VHDL Verification Methodology (OS-VVM).
Blue Pearl Software rolled out the latest release of their EDA software, Blue Pearl Software Suite, for Windows and Linux operating systems. Release 6.0 features enhancements that improve support for SystemVerilog and VHDL, as well as FPGA design. Release 6.0 improves support for SystemVerilog and VHDL and the FPGA synthesis flow. Designers can now mix and match hardware languages in the same design, with language checking that matches their downstream tools. Release 6.0 of Blue Pearl Software Suite is available now.
SynaptiCAD rolled out an upgraded version of WaveFormer Lite. WaveFormer Lite is an entry level tool that can generate VHDL and Verilog stimulus-based test benches for the Actel Libero design software and other FPGA/ASIC vendor flows without requiring any special runtime engines. WaveFormer Lite fits seamlessly into Actel’s design environment, automatically extracting signal information from your HDL design files, and producing HDL test bench code that can be used with any standard VHDL or Verilog simulator.
Thanks to a new OEM agreement between Altium and Aldec, Altium Designer will new feature Aldec’s FPGA simulation capabilities. As a result of the agreement, Aldec’s OEM simulator will be the default VHDL or Verilog FPGA simulation technology in the next release of Altium Designer, currently scheduled for release in the next few weeks.
Aldec introduces Active-HDL 8.2 sp1, which is a RTL and gate-level simulator for FPGA design and verification engineers. Active-HDL 8.2 sp1 includes full support for Xilinx SecureIP, IEEE VHDL/Verilog encrypted IP, and an enhanced Assertions bundle option. Active-HDL is a Windows FPGA design and simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. Active-HDL 8.2 sp1 is available today.