PLDA introduced their QuickUDP, which is a 10Gb UDP Hardware stack IP core for FPGA devices. The QuickUDP IP solution is a 100% RTL-designed IP, compliant with the IEEE802.3 specification and supports the ARP, IPv4, ICMP, IGMP, and UDP protocols. The PLDA QuickUDP 10G UDP Hardware Stack IP is available now from PLDA. The PLDA QuickUDP can be integrated into Altera-based and Xilinx-based FPGA designs.
CAST introduced the UDPIP IP core. The CAST UDPIP is a hardware implementation of the User Datagram Protocol (UDP), which is a fast, simple, transport layer protocol that works without the handshaking and error correction of the more rigorous Transmission Control Protocol (TCP). The UDPIP IP core is available now in Verilog or as an optimized netlist for Altera and Xilinx FPGAs. Integration with MAC cores from CAST, FPGA vendors, or other sources is available. Integration with CAST compression cores (e.g., the H.264 encoder) is also available.