Tag Archives: TSMC

Xilinx Implements First UltraScale ASIC Class Programmable Architecture

Xilinx UltraScale Architecture

Xilinx has taped out the semiconductor industry’s first 20nm device, and the PLD industry’s first 20nm All Programmable device. In addition, Xilinx has also implemented the industry’s first ASIC-class programmable architecture called UltraScale. According to Xilinx, the company is about a year ahead in delivering 1.5–2X more realizeable system-level performance and integration.

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Xilinx Announces Three First in 20nm All Programmable Devices

Xilinx 20nm product portfolio

Xilinx made three announcements about the execution and introduction of their next generation 20nm All Programmable Devices. The announcements are about the Xilinx Vivado Design Suite, tape out of their first 20nm product on TSMC’s 20SoC manufacturing process, and their first ten customer engagements on 20nm architecture evaluations and implementation activities.

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Altera Shares Plans for Next Generation 20nm Products

Altera Next Generation 20nm Products

Altera revealed plans for their next generation of 20nm products. According to the company, they will offer a system-integration platform that combines the hardware programmability of FPGAs with the software flexibility of digital signal processors and microprocessors along with the efficiencies of application-specific hard intellectual property (IP). Altera’s next-generation devices leverage TSMC’s 20nm process technology. 20nm system-on-chip (SoC) FPGAs provide engineers a software migration path from 28nm to 20nm while delivering a 50% processor subsystem performance increase.

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Synopsys, Altera, TSMC Team on Silicon-Accurate Parasitic Modeling and Extraction

Synopsys, Altera and TSMC teamed together to create silicon-accurate modeling of key parasitic effects in Synopsys’ StarRC solution for TSMC’s 28 nanometer (nm) processes. Altera has successfully deployed StarRC to achieve signoff accurate extraction and accelerate the design cycle of its 28nm FPGA designs. StarRC is now fully deployed as the signoff parasitic extraction solution for 28-nanometer Stratix V FPGA devices.

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Altera, TSMC Use CoWoS Process to Create Heterogeneous 3D IC Test Vehicle

Altera and TSMC teamed on a heterogeneous 3D IC test vehicle. The process uses TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process. Altera is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle using TSMC’s CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets.

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Altera FPGA Devices Feature TSMC 28HP and 28LP Processes

Altera will use two distinct 28nm process technologies. With their high-end FPGA family, Altera will continue to use TSMC’s 28-nm High Performance (28HP) process technology. However, now the company will use also TSMC’s 28nm Low-Power (28LP) process technology for Altera’s low-cost and midrange product families. Engineering samples of Altera’s 28-nm Stratix V FPGAs will be available to customers starting in the first quarter of 2011. Customers can start their Stratix V FPGA designs now by using Altera’s Quartus II software. Additional 28-nm FPGA families will be announced in 2011.

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Xilinx 28nm High-Performance, Low-Power Process for FPGA Devices

The exorbitant cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials, and the need for both hardware and software programmability, all in the face of rough economic times and reduced staffing – are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs. Xilinx calls the convergence of these trends the Programmable Imperative.

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