Tag Archives: Tools

Plunify Takes Altera Quartus II FPGA Tools to the Cloud

Plunify cloud platform for Quartus II tools

Plunify introduced the Altera Quartus II cloud platform for designing with Stratix, Cyclone and Arria FPGA devices. The cloud tool helps FPGA designers to accelerate chip design workflows, and save time and money in the process. Quartus II is an easy-to-use software platform for programmable logic design. The new relationship with Altera marks the production availability of Plunify’s cloud based solution for FPGA design.

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Microsemi Announces SmartFusion2 SoC FPGA Starter Kit

Microsemi SmartFusion2 Starter Kit

Microsemi introduced the SmartFusion2 SoC FPGA Starter Kit. The tool offers engineers a prototyping platform for the Microsemi SmartFusion2 system-on-chip (SoC) field programmable gate arrays (FPGAs). The kit supports interfaces like Ethernet, USB, SPI, I2C and UART. It includes a comprehensive breadboard to support unique design requirements.

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Synopsys Synplify r2012.09 Synthesis Tools Reduce FPGA Implementation Time

Synopsys Synplify Pro and Synplify Premier FPGA synthesis tools v2012.09

Synopsys released the newest version of their Synplify Pro and Synplify Premier FPGA synthesis tools. The 2012.09 release of Synplify includes new multiple error isolation and incremental fix capabilities that accelerate FPGA implementation. The features enable FPGA designers and engineers deploying FPGA-based prototypes such as Synopsys’ HAPS systems to speed design project schedules by weeks.

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MathWorks EDA Simulator Link v3.3

MathWorks rolled out version 3.3 of their EDA Simulator Link. The latest version features FPGA-in-the-loop (FIL) capabilities for Xilinx FPGA development boards. FIL enables engineers to verify their designs at hardware speeds while using Simulink as a system-level test bench. EDA Simulator Link v3.3 is available now with prices starting at $2000 (US list price).

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PLDA EZDMA IP Solution

The PLDA’s EZDMA IP is a DMA solution. The IP features a vendor-agnostic user interface and seamless device migration. It is configurable for resource optimization and customizable to fit specific customer requirements. The PLDA EZDMA solution supports the Aldec Riviera-PRO for Linux and Active-HDL for Windows verification tools for FPGA development. PLDA’s EZDMA IP solution is available now for PCI Express Gen1 and Gen2 designs.

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Best Tools for Verification and Debug of FPGAs

At ESC Boston, GateRocket will conduct a class, Best Tools for Verification and Debug of FPGAs. The course will be presented by Dave Orecchio, President and CEO of GateRocket, a supplier of FPGA design and debug solutions for Xilinx and Altera programmable devices. The event will take place at 3:15 pm, Wednesday, September 22, 2010 in Room 103, Hynes Convention Center, Boston.

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Lattice Diamond Design Software for FPGA Devices

Lattice Semiconductor launched their Lattice Diamond FPGA design software for Lattice FPGA products. Lattice Diamond software is a set of tools, efficient design flows and modern user interface that enables designers to more quickly target low power, cost sensitive FPGA applications. The Diamond software allows designers to efficiently manage multiple implementations in one project. Diamond features an accurate power calculator, simultaneous switching output noise calculator, and the MAP and PAR FPGA implementation algorithms. The Lattice Diamond software is available now for download for both Windows and Linux.

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Impulse C-to-FPGA Tools Integrates with DRC Accelium Coprocessor Card

DRC Computer and Impulse Accelerated Technologies have integrated the Impulse C-to-FPGA tools with the DRC Accelium coprocessor card. The integration enables software engineers to fully access hardware acceleration using familiar C programming methods. It provides C-language control of I/O, memory, streams and signals at the hardware level, allowing applications to leverage the high parallelism possible in FPGAs for higher performance.

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Xilinx ISE Design Suite 12

Xilinx announced version 12 of the ISE Design Suite. The latest version of the ISE design tools feature intelligent clock-gating technology that reduces dynamic power consumption by as much as 30%. ISE Design Suite 12 includes timing-driven design preservation, AMBA 4 AXI4-compliant IP support for plug-and-play design, and an intuitive design flow with fourth-generation partial reconfiguration capabilities that lowers system cost for a broad range of high performance applications. ISE Design Suite 12 is now available for all ISE Editions. List price starts at US$2,995 for the Logic Edition.

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Synopsys Synplify Pro FPGA Synthesis Tool Supports Actel SmartFusion

Synopsys announced enhanced FPGA synthesis support for Actel’s new SmartFusion intelligent mixed signal FPGAs. The enhanced version of Synopsys’ Synplify Pro FPGA synthesis tool is available now. Engineers who have obtained Synplify Pro software through the Actel Libero Integrated Develop Environment or directly from Synopsys will receive support for SmartFusion devices at no extra cost.

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