Tag Archives: Tool

Breker Verification Systems Launches TrekSoC-Si for Testing FPGA Prototypes

Breker Verification Systems introduced their TrekSoC-Si tool for automatically generates multi-threaded, multi-processor, self-verifying C test cases that run on the SoC’s embedded processors on in-circuit emulation (ICE) platforms, field programmable gate array (FPGA) prototypes and production silicon. The tool eliminates the need to hand-write tests for embedded processors in simulation and acceleration. TrekSoC-Si is shipping now.

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Create Fastest FPGA Designs with Altera Quartus II Software v13.0

Altera Quartus II software v13.0

Altera released version 13.0 of their Quartus II software. Quartus II v13 enables designs targeting Stratix V FPGAs to achieve the fastest Fmax of any FPGA in the industry with a two speed-grade advantage over the nearest competitor. Both the Subscription Edition and the free Web Edition of Quartus II software v13.0 are now available for download.

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Altera Cyclone V GX FPGA Development Kit for 28nm Designs

Altera Cyclone V GX FPGA development board

Altera recently introduced their Cyclone V GX FPGA development kit. It is based on the industry’s lowest-power, lowest-cost 28nm FPGA. Altera’s 28nm development kits increase designer productivity by offering the tools and resources necessary to get 28nm FPGAs developed and integrated into systems. The 28 nm development kits include FPGA boards, hardware and cables, and development software that provide access to a variety of IP cores, reference designs and documentation. The Altera Cyclone V GX FPGA Development Kit is available now for $1,199.

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Flexras Technologies Introduces Wasga Compiler

Flexras Wasga Compiler screenshot

Flexras Technologies launched their Wasga Compiler. The automatic partitioning tool increases multi-FPGA design by a factor of ten. Wasga Compiler complements FPGA-based SoC prototyping. The software tool features high clock frequencies, fast execution time, and unlimited design capacity. It supports multi-billion ASIC gates equivalents designs, and maps them to any Altera or Xilinx board. Wasga Compiler is available now.

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Lattice Semiconductor PAC-Designer Mixed Signal Design Software v6.2

Lattice Semiconductor rolled out version 6.2 of their PAC-Designer mixed signal design software. PAC-Designer 6.2 features updated support for Lattice’s Platform Manager, Power Manager II and ispClock devices, reduced LogiBuilder code size, simplified design flow and better access to external Platform Manager pin-to-pin connections. PAC-Designer v6.2 can be downloaded now for free. PAC-Designer 6.2 software does not require a separate license file.

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Aldec Active-HDL v9.1 FPGA Design and Simulation Tool

Aldec launched verion 9.1 of the Active-HDL FPGA Design and Simulation solution. Active-HDL v9.1 features auto-complete technology built into the HDL Editor, language templates, phrase highlighting, enhanced level of automation, and new HDL code browser tool that can detect errors in the source code even before compilation. The HDL-based tool supports design creation and simulation of the newest FPGA devices from Altera, Atmel, Lattice, Microsemi (Actel), Tabula, Quicklogic and Xilinx.

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Altera Arria V Early Power Estimator Tool

Altera introduced their Arria V PowerPlay Early Power Estimator (EPE) tool. As the name implies, Arria V EPE enables designers to accurately evaluate the power consumption savings that can be achieved using Arria V FPGA devices. Arria V FPGAs offer the lowest total power for midrange applications with an optimized balance between power, performance and price. The Arria V architecture has been tailored to maintain current performance while providing power savings.

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Altera Quartus II Software v11.0

Altera launched version 11 of their Quartus II software for CPLD, FPGA and HardCopy ASIC designs. Quartus II v11 features the Qsys, expanded support for the Stratix V FPGA family, faster board bring-up, new performance monitoring capabilities in the external memory interface toolkit and improved usability with the Transceiver Toolkit. Both the Subscription Edition and the free Web Edition of Quartus II software version 11.0 are now available. Subscribers receive Quartus II software, the ModelSim-Altera Starter edition and a full license to the IP Base Suite. The annual software subscription is $2,995 for a node-locked PC license.

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Lattice Diamond FPGA Design Software Tool Suite v1.2

Lattice Semiconductor rolled out version 1.2 of their Lattice Diamond FPGA design software tool suite. The Lattice Diamond v1.2 software for both Windows and Linux is available now. The Lattice Diamond free license features access to many Lattice devices, such as the MachXO2 and MachXO PLD families, the LatticeXP2 FPGA family and the LatticeECP2 FPGA family. The Lattice Diamond subscription license adds support for all Lattice FPGAs, including the LatticeECP3 devices. The Lattice Diamond subscription license price is $895 per year.

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Altera Qsys System Integration Tool

Altera’s Qsys is a system-integration tool for FPGA designers. Qsys automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. Qsys features the industry’s first FPGA-optimized network-on-chip-based interconnect. Qsys offers memory-mapped and streaming interface support that achieves nearly double the performance of Altera’s SOPC Builder tool, while improving system scalability for large FPGA designs and enabling support for industry-standard interfaces (Avalon and AMBA AXI and AHB standards from ARM, etc). A beta release of Qsys is available in Quartus II Subscription Edition software v10.1

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