Tag Archives: Synopsys

Synopsys HAPS-70 FPGA-based Prototyping System Features Xilinx Virtex-7

Synopsys HAPS-70 Series FPGA-based prototyping systems for system-on-chip (SoC) designs

Synopsys introduced the HAPS-70 Series FPGA-based prototyping systems for system-on-chip (SoC) designs. The HAPS-70 FPGA-based prototyping systems are available now in nine model variants. Capacities range from 12 to 144 million ASIC gates. The series consists of the HAPS-70 S12, HAPS-70 S24, HAPS-70 S36, HAPS-70 S48, HAPS-70 S60, HAPS-70 S72, HAPS-70 S96, HAPS-70 S120 and HAPS-70 S144. The S denotes ASIC Gate count support.

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Synopsys Debuts Deep Trace Debug for HAPS FPGA-based Prototyping Systems

Synopsys Deep Trace Debug feature for HAPS FPGA-based prototyping systems

Synopsys rolled out a new Deep Trace Debug feature for their HAPS FPGA-based prototyping systems. HAPS Deep Trace Debug increases productivity for debugging complex SoCs by enabling prototypers to capture the long signal trace history needed to identify the root cause of design bugs. HAPS Deep Trace Debug support in Synopsys’ Identify RTL debugger software and HAPS Deep Trace Debug SRAM daughter boards is available now.

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Synopsys Synplify FPGA Synthesis Tools v2012.03 Reduce Runtime by 30%

Synopsys launched version 2012.03 of their Synplify Pro and Synplify Premier FPGA synthesis tools. The new Synplify 2012.03 products include a new continue-on-error feature, hierarchical design techniques, and improved algorithms that deliver faster runtimes. The latest Synplify Pro and Synplify Premier synthesis software is available now. Customers with a current maintenance agreement can download the 2012.03 release from Synopsys using their SolvNet account. The Synplify FPGA synthesis products are supported on Windows and Linux, 32 and 64-bit platforms.

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Synopsys, Altera, TSMC Team on Silicon-Accurate Parasitic Modeling and Extraction

Synopsys, Altera and TSMC teamed together to create silicon-accurate modeling of key parasitic effects in Synopsys’ StarRC solution for TSMC’s 28 nanometer (nm) processes. Altera has successfully deployed StarRC to achieve signoff accurate extraction and accelerate the design cycle of its 28nm FPGA designs. StarRC is now fully deployed as the signoff parasitic extraction solution for 28-nanometer Stratix V FPGA devices.

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Blue Pearl Software Suite Supports Synopsys Synplify Pro FPGA Synthesis

Blue Pearl Software Suite now supports Synopsys’ Synplify Pro FPGA synthesis software for VHDL and SystemVerilog designs. Blue Pearl Software collaborated with Synopsys to create an optimized flow that works with Synplify Pro FPGA synthesis software. VHDL and SystemVerilog designers are now able to automatically generate an exhaustive set of constraints that address false and multi-cycle paths and that work with Synopsys’ synthesis flow.

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New Certify Multi-FPGA ASIC Prototyping Software and Identify RTL Debugger

Synopsys released the latest version of their Certify multi-FPGA ASIC prototyping software and Identify RTL Debugger. The new release of Identify and Certify FPGA software tools feature an improved flow, which results in higher productivity for users of Synopsys’ HAPS FPGA-based prototyping systems. It also ensure that engineers who build their own hardware prototypes can do so faster and with less effort. The latest release of Identify and Certify FPGA-based prototyping tools are available now.

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Altera SoC FPGA Virtual Target

Altera introduced the SoC FPGA Virtual Target. It is a PC-based functional simulation of the Altera SoC FPGA development board. The SoC FPGA Virtual Target is the industry’s first virtual target designed to enable immediate device-specific embedded software development targeting Altera’s newly announced SoC FPGA devices. The Altera SoC FPGA Virtual Target can be ordered now. FPGA-in-the-loop extension is planned for early 2012.

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Synplify Pro and Synplify Premier FPGA Synthesis Tools, 2011.09 Release

Synopsys rolled out the 2011.09 software release of Synplify Pro and Synplify Premier FPGA synthesis tools. The latest version enables engineers to build higher reliability into FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs). The 2011.09 release of the Synplify Pro and Synplify Premier synthesis tools is available now.

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Synplify Tools Feature FPGA Synthesis Support for Xilinx IDS 13

Synopsys Synplify Pro, Synplify Premier and Synphony now offers synthesis support for the Xilinx ISE Design Suite (IDS) v13, which provides support for their 28-nanometer (nm) 7 series FPGAs. The Synopsys synthesis tools feature a hierarchical project manager that enables team-design collaboration with a mixed bottom-up/top-down approach that is integrated with Xilinx’s SmartGuide incremental place and route (P&R) technology. The updated FPGA synthesis tools are available now.

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Synopsys HAPS-600 High Capacity FPGA-Based Prototyping Systems

Synopsys introduced the HAPS-600 FPGA-based prototyping systems. The HAPS-600 series supports up to 81 million ASIC gates equivalent. The Synopsys solution is based on Xilinx Virtex-6 LX760 FPGA devices and offers performance up to 200 megahertz (MHz). The HAPS-600 series features native support of co-simulation, transaction-based verification and links to virtual prototyping via the UMRBus communication interface. The prototyping systems enable high debug visibility earlier in the design cycle. The HAPS-600 series is available now.

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