Tag Archives: Stratix

Impulse CoDeveloper v3.7 Compiles ANSI C to Altera Quartus Qsys r12

Impulse Accelerated Technologies released version 3.7 of their Impulse C and CoDeveloper for compiling C algorithms to Altera’s Quartus revision 12 Qsys software. This enables software developers to more easily compile C based algorithms for the fastest integration into Altera Stratix and Cyclone FPGAs. According to Impulse, project managers report 50% time savings on first prototype and more than 80% time savings on iterations using the Impulse C tool to Quartus tool flow.

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Altera Rolls Out 40-Gbps and 100-Gbps Ethernet Intellectual Property Cores

Altera 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE) intellectual property (IP) cores

Altera announced the production availability of their 40-Gbps Ethernet and 100-Gbps Ethernet intellectual property cores. The cores can be used to create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs. Altera’s 40GbE and 100GbE IP cores are compatible with the recently announced Quartus II software v12.0. They are available for download on the Altera website.

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Altera EFEC7 and EFEC20 100G IP Cores

Altera introduced the EFEC7 and EFEC20 enhanced forward error correction (EFEC) IP cores. The multi-dimensional IP cores are optimized for high performance Stratix IV and Stratix V series FPGA devices. The EFEC7 and EFEC20 were developed by Altera’s Newfoundland Technology Centre (formerly Avalon Microelectronics). They are ideal for 100G applications such as metro and long-haul optical transport networks (OTN). According to Altera, they are the first company to offer an integrated, single source 100G solution.

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GiDEL PROC_SoC 3-4S and PROC_SoC 10-4S ASIC Prototyping Systems

The GiDEL PROC_SoC 3-4S and PROC_SoC 10-4S ASIC prototyping systems feature the Altera Stratix IV E FPGA. The PROC_SoC 3 and PROC_SoC 10 are designed to debug and verify advanced SoC designs. The PROC_SoC 3-4S supports designs up to 36 million ASIC gates and the PROC_SoC 10-4S supports designs up to 120 million ASIC gates. Both ASIC prototyping systems can be connected to support for up to 360 million ASIC gates. The systems are architected and designed to operate at system clock speeds up to 300MHz.

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Altera Quartus II Software Version 10.0 for CPLD, FPGA, HardCopy ASIC

Altera announced version 10.0 of their Quartus II development software for CPLD, FPGA and HardCopy ASIC designs. Quartus II software v10.0 features 2X to 3X faster compile times than the nearest competitor for high-density designs. The latest software release includes support for Altera’s 28-nm Stratix V FPGA family and offers several new productivity features that enable design teams to achieve faster timing closure and shorten time to market. Both the Subscription Edition and the free Web Edition of Quartus II software v10.0 are now available for download.

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National Association of Broadcasters Show Features Altera FPGAs

At the 2010 National Association of Broadcasters (NAB) Show, Altera will showcase a range of FPGA devices and complete solutions for the broadcast industry. At the show, Altera will demonstrate the broadcast performance capabilities of Cyclone, Arria, and Stratix FPGA families and HardCopy ASICs. Altera’s FPGA and ASIC devices help designers achieve optimal price, performance, and power for broadcast applications. 2010 NAB will take palce in Las Vegas Convention Center from Monday, April 12, to Thursday, April 15, 2010.

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Jointwave H.264 Encoder IP Cores

Jointwave introduced their H.264 series encoder IP core. The Jointwave IP cores support Level 1.0 to 5.1 of H.264 (MPEG-4 Part 10, also called AVC). The cores cover baseline profile, main profile, and high 4:2:2/4:4:4 profile. Compare to competitors’ solutions, Jointwave’s IP core uses less hardware resources. The H.264 encoder features ultra-low frequency, super low latency, small die size, and ultra-low power consumption. Jointwave H.264 IP core can be used without embedded or external CPU, and reduce the system complexity. It runs on FPGA and ASIC.

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