Altera has completed interoperability testing between their Stratix IV GT FPGA and the MoSys Bandwidth Engine device in a serial memory application. Stratix IV GT FPGA devices leverage the GigaChip Interface to interoperate with MoSys’s Bandwidth Engine device. Altera is the first FPGA vendor to deliver device support for the GigaChip Interface. The interoperability gives 100G wireline application designers a high-performance, high-bandwidth memory solution.
Altera announced the interoperability of the Stratix IV GT FPGAs with 40G Quad Small Form-Factor Pluggable (QSFP) optical modules from Avago Technologies. The 11.3-Gbps transceivers of the Stratix IV GT FPGAs enable designers to connect eight QSFP optical modules to a single FPGA and transport up to 320 Gbps of aggregate data in their system. Obtaining this same level of performance using FPGAs with sub-10-Gbps transceivers would normally require 32 SFP+ optical modules.
Altera Stratix IV FPGAs passed the Interlaken Alliance’s device interoperability testing. Altera certified their FPGAs interface with third-party components using the Interlaken protocol. Stratix IV GT FPGAs passed interoperability testing at 6.25-Gbps line rates. According to Altera, their FPGA devices are the only Interlaken solution capable of supporting line rates of 10 Gbps. Device interoperability testing validates Stratix IV FPGAs for chip-to-chip Interlaken interface and ensures they can be quickly deployed as a turnkey solution for next-generation wireless and wireline infrastructure applications.
The Altera Stratix IV GT EP4S100G2 FPGA is now shipping in volume production. The Stratix IV GT EP4S100G2 FPGAs feature integrated 11.3-Gbps transceivers. The EP4S100G2 FPGAs meet the high-speed bandwidth requirements for next-generation framer, MAC, bridging and switching applications for 100-Gigabit Ethernet (GbE), and 100-Gigabit Optical Transport Networks (OTN). Altera’s 100G solutions help communications systems designers developing 100G systems to accelerate their time to market and reduce risk compared to ASICs, ASSPs and other currently available FPGA technologies.