Tag Archives: SRIO

LatticeECP3 AMC Evaluation Platform

Lattice Semiconductor introduced the LatticeECP3 AMC evaluation platform for their Serial RapidIO 2.1 endpoint IP core. The LatticeECP3 AMC evaluation platform helps engineers to investigate and experiment with the features of the LatticeECP3 SERDES and SRIO core. The board features a single AMC module card edge interface, common options interface, and a Vita 57.1 FPGA Mezzanine Card (FMC) expansion connector. The evaluation and demonstration platform is based on the Advanced Mezzanine Card (AMC) form factor. The Serial RapidIO 2.1 IP core and AMC platform are available now.

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Serial RapidIO 2.1 Endpoint Soft IP Core for LatticeECP3 FPGA

Lattice Semiconductor has licensed the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family from Praesum. Lattice has full rights to use and sub-license the Serial RapidIO IP core. The core supports 1x, 2x, and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO solution in the industry. The Serial RapidIO 2.1 IP core is available for immediate evaluation and use.

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