Breker Verification Systems introduced their TrekSoC-Si tool for automatically generates multi-threaded, multi-processor, self-verifying C test cases that run on the SoC’s embedded processors on in-circuit emulation (ICE) platforms, field programmable gate array (FPGA) prototypes and production silicon. The tool eliminates the need to hand-write tests for embedded processors in simulation and acceleration. TrekSoC-Si is shipping now.
Aldec launched verion 9.1 of the Active-HDL FPGA Design and Simulation solution. Active-HDL v9.1 features auto-complete technology built into the HDL Editor, language templates, phrase highlighting, enhanced level of automation, and new HDL code browser tool that can detect errors in the source code even before compilation. The HDL-based tool supports design creation and simulation of the newest FPGA devices from Altera, Atmel, Lattice, Microsemi (Actel), Tabula, Quicklogic and Xilinx.
MathWorks introduced xPC Target 5.0. The real-time rapid control prototyping and hardware-in-the-loop simulation tool now includes support for FPGA devices. With xPC Target, computationally intensive algorithms can now run on FPGA boards. Control systems engineers can now program FPGA boards for xPC Target Turnkey systems using code generated by Simulink HDL Coder. xPC Target is available now with prices starting at $4,000.
MathWorks rolled out version 3.3 of their EDA Simulator Link. The latest version features FPGA-in-the-loop (FIL) capabilities for Xilinx FPGA development boards. FIL enables engineers to verify their designs at hardware speeds while using Simulink as a system-level test bench. EDA Simulator Link v3.3 is available now with prices starting at $2000 (US list price).
Aldec’s Hardware-Assisted Simulation (HES) platform now features Mirror-Box debugging technology. Mirror-Box debugging technology streamlines debugging during hardware-assisted simulation. The Mirror-Box technology enables any component, at any hierarchical level, to be mirrored so that two implementations of the same component can be simulated: one implementation is the original RTL code which resides in the HDL Simulator and the other is its FPGA counterpart which resides in the hardware board.
InPA Systems, Inc. is officially being launched today. The company was formed to develop and market FPGA-based rapid prototyping technology to engineers. The company integrates RTL simulation, hardware and software debug environments, provides an Active Debug methodology and enables full visibility into the multi-FPGA prototype to compress the time it takes to debug SoC designs. InPA Systems’ patent pending Active Debug feature full visibility technology to better detect hardware faults and reduce the FPGA P&R iterations associated with the debug cycle for next-generation complex SoCs.
Thanks to a new OEM agreement between Altium and Aldec, Altium Designer will new feature Aldec’s FPGA simulation capabilities. As a result of the agreement, Aldec’s OEM simulator will be the default VHDL or Verilog FPGA simulation technology in the next release of Altium Designer, currently scheduled for release in the next few weeks.
EMA Design Automation announced the OrCAD/Aldec FPGA Bundles. The FPGA design and simulation bundle for OrCAD is a complete flow for PCB and FPGA design. The FPGA bundles enable Cadence OrCAD users to add FPGA design and simulation capabilities from Aldec. Prices for the bundles start at $1,756. Aldec Active-HDL tools provide high performance, mixed-language FPGA design and simulation that operates at a minimum of twice the speed of FPGA vendor tools.
The QPACE supercomputer, which features Xilinx Virtex-5 LX110T FPGA devices, is used in the study of Quantum Chromodynamics. The main simulation process used to model Quantum Chromodynamics is known as Lattice QCD and is only possible using high-powered, highly parallel supercomputers. Xilinx Virtex-5 LX110T FPGAs were selected to provide core networking technology in QPACE.
Aldec introduces Active-HDL 8.2 sp1, which is a RTL and gate-level simulator for FPGA design and verification engineers. Active-HDL 8.2 sp1 includes full support for Xilinx SecureIP, IEEE VHDL/Verilog encrypted IP, and an enhanced Assertions bundle option. Active-HDL is a Windows FPGA design and simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. Active-HDL 8.2 sp1 is available today.