Xilinx recently introduced the Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE, CPRI v4.1 LogiCORE, and JESD204B v.1.1 LogiCORE IP cores. The Xilinx three LogiCORE IP cores support connectivity standards and will help developers address design challenges in building new wireless equipment with higher system capacities. The Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP, JESD204 v1.1 LogiCORE IP , and CPRI v4.1 LogiCORE IP are ideal for building programmable, flexible and cost effective 3G+/4G wireless base stations. They are available in Xilinx’s ISE Design Suite 13.3 and can be evaluated free of charge.
Altera introduced their RapidIO MegaCore Function IP core. It is implemented in a Stratix IV GX FPGA with a Serial RapidIO Gen 2 switch from Integrated Device Technology (IDT). The IP core is the first Serial RapidIO Gen2 FPGA-based solution. The RapidIO MegaCore Function IP core is available now for download. It is available as encrypted IP or as source code for complete user control.
Lattice Semiconductor has extended the Serial RapidIO 2.1, Level 1 endpoint core to support 4 x 3.125Gbps. The previous version of the LatticeECP3 FPGA IP core supported 1x and 2x up to 3.125Gbps and 4x up to 2.5Gbps. The Lattice core can be used with the Lattice Advanced Mezzanine Card (AMC) form factor platform. The Serial RapidIO 2.1 IP core and associated AMC platform are available now for evaluation and use.
Lattice Semiconductor introduced the LatticeECP3 AMC evaluation platform for their Serial RapidIO 2.1 endpoint IP core. The LatticeECP3 AMC evaluation platform helps engineers to investigate and experiment with the features of the LatticeECP3 SERDES and SRIO core. The board features a single AMC module card edge interface, common options interface, and a Vita 57.1 FPGA Mezzanine Card (FMC) expansion connector. The evaluation and demonstration platform is based on the Advanced Mezzanine Card (AMC) form factor. The Serial RapidIO 2.1 IP core and AMC platform are available now.
Lattice Semiconductor has licensed the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family from Praesum. Lattice has full rights to use and sub-license the Serial RapidIO IP core. The core supports 1x, 2x, and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO solution in the industry. The Serial RapidIO 2.1 IP core is available for immediate evaluation and use.