Tag Archives: RTL

PLDA QuickUDP 10Gb UDP Hardware Stack IP Core for Altera and Xilinx FPGAs

PLDA QuickUDP 10Gb UDP Hardware stack IP core for FPGA devices

PLDA introduced their QuickUDP, which is a 10Gb UDP Hardware stack IP core for FPGA devices. The QuickUDP IP solution is a 100% RTL-designed IP, compliant with the IEEE802.3 specification and supports the ARP, IPv4, ICMP, IGMP, and UDP protocols. The PLDA QuickUDP 10G UDP Hardware Stack IP is available now from PLDA. The PLDA QuickUDP can be integrated into Altera-based and Xilinx-based FPGA designs.

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Xilinx Introduces Vivado Design Suite 2012.2

Xilinx Vivado Design Suite 2012.2

Xilinx announced Vivado Design Suite 2012.2. This is the first public release of their next-generation design environment. The Xilinx Vivado Design Suite is an IP and system-centric design environment built from the ground up to accelerate the design of not only programmable logic and I/O but all programmable devices. The Vivado Design Suite 2012.2 is now available at no additional cost to all ISE Design Suite customers who are currently in warranty.

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SpringSoft ProtoLink Probe Visualizer

SpringSoft announced their ProtoLink Probe Visualizer. The tool increases design visibility and simplifies debugging of FPGA-based prototype boards. ProtoLink Probe Visualizer achieves a high level of design visibility and makes prototype boards easier to debug starting at the early RTL design stage all the way through final implementation. The tool shortens the verification cycle of off-the-shelf or custom-designed prototypes. The ProtoLink Probe Visualizer is available now for a list price of $40,000 (USD) for a one-year subscription license.

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InPA Systems Develops Active Debug Technology for Rapid Prototyping

InPA Systems, Inc. is officially being launched today. The company was formed to develop and market FPGA-based rapid prototyping technology to engineers. The company integrates RTL simulation, hardware and software debug environments, provides an Active Debug methodology and enables full visibility into the multi-FPGA prototype to compress the time it takes to debug SoC designs. InPA Systems’ patent pending Active Debug feature full visibility technology to better detect hardware faults and reduce the FPGA P&R iterations associated with the debug cycle for next-generation complex SoCs.

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Actel Libero Features Access to Over 50 IP Cores

Actel’s Libero Gold and Platinum editions now include access to over fifty IP cores. The Libero Gold Edition, which supports Actel FPGAs up to 1.5 million system gates, includes obfuscated versions of the Actel IP cores that can be easily used in designs but cannot be modified. The Libero Platinum edition supports Actel FPGA devices above 1.5 million system gates, such as AGLE3000, M1AGLE3000, A3PE3000, M1A3PE3000, A3PE3000L, RT3PE3000L, RTAX2000S, RTAX4000S, RTAX2000D, RTAX4000D, and AX2000.

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RocketDrive FPGA Verification and Debug Solution Supports Virtex-6

The latest versions of GateRocket’s RocketDrive FPGA verification and debug solution will roll out in July 2010. RocketDrive reduces verification and debug time by integrating the FPGA into the HDL simulator to provide a “hardware in the loop” process based on GateRocket’s Device Native methodology. This technique combines the actual FPGA hardware and RTL simulation models in the same verification run and allows execution of the design on the target FPGA device. The new version features support for Xilinx Virtex-6 programmable devices. Pricing starts at $25,000.

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Altium Designer Features Aldec FPGA Simulation Technology

Thanks to a new OEM agreement between Altium and Aldec, Altium Designer will new feature Aldec’s FPGA simulation capabilities. As a result of the agreement, Aldec’s OEM simulator will be the default VHDL or Verilog FPGA simulation technology in the next release of Altium Designer, currently scheduled for release in the next few weeks.

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BDTI Certified Results for Synfora PICO High-Level Synthesis Tool

An FPGA-based implementation of a complex video motion analysis algorithm (BDTI Optical Flow application) using Synfora’s PICO C synthesis tools outperformed a traditional DSP processor implementation on throughput by a factor over 40x achieving a processing rate of 204 frames per second and provided a 30X price/performance advantage over DSPs. The PICO implementation required fewer code modifications to the reference code than the DSP implementation to achieve the best performance.

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Aldec Active-HDL 8.2 sp1 Supports Xilinx SecureIP

Aldec introduces Active-HDL 8.2 sp1, which is a RTL and gate-level simulator for FPGA design and verification engineers. Active-HDL 8.2 sp1 includes full support for Xilinx SecureIP, IEEE VHDL/Verilog encrypted IP, and an enhanced Assertions bundle option. Active-HDL is a Windows FPGA design and simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. Active-HDL 8.2 sp1 is available today.

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